EPF6016TC144-3 Altera, EPF6016TC144-3 Datasheet

IC FLEX 6000 FPGA 16K 144-TQFP

EPF6016TC144-3

Manufacturer Part Number
EPF6016TC144-3
Description
IC FLEX 6000 FPGA 16K 144-TQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet

Specifications of EPF6016TC144-3

Number Of Logic Elements/cells
1320
Number Of Labs/clbs
132
Number Of I /o
117
Number Of Gates
16000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-1282

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Features...
Note:
(1)
Altera Corporation
A-DS-F6000-04.1
March 2001, ver. 4.1
Typical gates
Logic elements (LEs)
Maximum I/O pins
Supply voltage (V
Table 1. FLEX 6000 Device Features
The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates.
Feature
(1)
CCINT
)
System-level features
Provides an ideal low-cost, programmable alternative to high-
volume gate array applications and allows fast design changes
during prototyping or design testing
Product features
EPF6010A
10,000
3.3 V
880
102
Register-rich, look-up table- (LUT-) based architecture
OptiFLEX
Typical gates ranging from 5,000 to 24,000 gates (see
Built-in low-skew clock distribution tree
100% functional testing of all devices; test vectors or scan chains
are not required
In-circuit reconfigurability (ICR) via external configuration
device or intelligent controller
5.0-V devices are fully compliant with peripheral component
interconnect Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
MultiVolt
between systems operating at different voltages
Low power consumption (typical specification less than 0.5 mA
in standby mode)
3.3-V devices support hot-socketing
®
TM
®
architecture that increases device area efficiency
I/O interface operation, allowing a device to bridge
EPF6016
16,000
1,320
5.0 V
204
EPF6016A
16,000
Programmable Logic
1,320
3.3 V
171
FLEX 6000
Device Family
EPF6024A
24,000
Data Sheet
1,960
3.3 V
Table
218
1)
1

Related parts for EPF6016TC144-3

EPF6016TC144-3 Summary of contents

Page 1

... Supply voltage (V ) 3.3 V CCINT Note: (1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates. Altera Corporation A-DS-F6000-04.1 ® Register-rich, look-up table- (LUT-) based architecture ® OptiFLEX architecture that increases device area efficiency Typical gates ranging from 5,000 to 24,000 gates (see Built-in low-skew clock distribution tree 100% functional testing of all devices ...

Page 2

... Flexible interconnect – – – – – ■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 ■ Flexible package options – – – – ■ Additional design entry and simulation support provided by ...

Page 3

... Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file. Table 3. FLEX 6000 Device Performance for Common Designs ...

Page 4

... The Altera software provides EDIF and LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools ...

Page 5

... FLEX 6000 devices includes all LUTs and registers. LEs are combined into groups called logic array blocks (LABs); each LAB contains 10 LEs. The Altera software automatically places related LEs into the same LAB, minimizing the number of required interconnects. Each LAB can implement a medium-sized block of logic, such as a counter or multiplexer. Signal interconnections within FLEX 6000 devices— ...

Page 6

... FLEX 6000 architecture, and facilitates efficient routing with optimum device utilization and high performance. 6 IOEs Row FastTrack Interconnect Row FastTrack Interconnect Column FastTrack Interconnect Local Interconnect (Each LAB accesses two local interconnect areas.) Logic Elements Altera Corporation ...

Page 7

... In addition, counters may also have synchronous clear or load signals design that uses non-global clock and clear signals, inputs from the first LAB are re-routed to drive the control signals for that LAB. See Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Figure 2. ...

Page 8

... LUT, which is a function generator that can quickly implement any function of four variables contains a programmable flipflop, carry and cascade chains. Additionally, each LE drives both the local and the FastTrack Interconnect. See LABCTRL1/ LABCTRL2 SYNCLR CLK1/SYNLOAD CLK2 LAB-wide control signals (SYNCLR and SYNLOAD signals are used in counter mode). Figure 4. Altera Corporation ...

Page 9

... LAB and all LABs in the same half of the row. Because extensive use of carry and cascade chains can reduce routing flexibility, these chains should be limited to speed-critical portions of a design. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Register Bypass Carry-In ...

Page 10

... This feature allows the FLEX 6000 architecture to implement high-speed counters, adders, and comparators of arbitrary width. Carry chain logic can be created automatically by the Altera software during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of carry chains for the appropriate functions ...

Page 11

... Figure 5. Carry Chain Operation Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Carry-In LUT Carry Chain LUT Carry Chain LUT Carry Chain LUT Carry Chain s1 Register LE 2 Register Register Register Carry-Out ...

Page 12

... LEs. Each additional LE provides four more inputs to the effective width of a function, with a delay as low as 0.5 ns per LE. Cascade chain logic can be created automatically by the Altera software during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of cascade chains for the appropriate functions ...

Page 13

... LAB-wide signals provide clock, asynchronous clear, synchronous clear, and synchronous load control for the register. The Altera software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers ...

Page 14

... LEs other than the second LAB. (3) The LAB-wide synchronous clear and LAB-wide synchronous load affect all registers in an LAB. 14 Cascade-In PRN D CLRN Cascade-Out Cascade-In PRN D Q CLRN Cascade-Out LAB-Wide Synchronous LAB-Wide Synchronous (3) (3) Load Clear Cascade-In PRN D CLRN Carry-Out Cascade-Out LE-Out Q LE-Out LE-Out Q Altera Corporation ...

Page 15

... In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a 4-input LUT. The Altera software automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade- in signal to form a cascade chain through the cascade-out signal ...

Page 16

... Either LABCTRL1 or LABCTRL2 can control the asynchronous clear or preset. Because the clear and preset functions are active-low, the Altera software automatically assigns a logic high to an unused clear or preset signal. The clear and preset logic is implemented in either the ...

Page 17

... In addition to the two clear and preset modes, FLEX 6000 devices provide a chip-wide reset pin (DEV_CLRn) that can reset all registers in the device. The option to use this pin is set in the Altera software before compilation. The chip-wide reset overrides all other control signals. Any register with ...

Page 18

... To/From 10 Adjacent LAB 5 10 through 10 Local Interconnect (32 Channels) Note: (1) For EPF6010A, EPF6016, and EPF6016A devices 144 channels and channels; for EPF6024A devices 186 channels and channels Column Interconnect (m Channels) (1) Figure 9 shows through To/From Adjacent 5 LAB through LE 10 Altera Corporation ...

Page 19

... LABs LEs, via the local interconnect. The row-to-local multiplexers are used more efficiently, because the multiplexers can now drive two LABs. column interconnects. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Figure 10 shows how an LAB connects to row and ...

Page 20

... Each LE output signal driving drive two column the FastTrack Interconnect can channels. drive two column channels Column Interconnect Any column channel can drive six row channels can be driven by any signal from two local interconnect areas. Row Interconnect From Adjacent Local Interconnect Altera Corporation ...

Page 21

... FastTrack Interconnect and do not receive any advantage from being routed on global signals. This LE-driving-global control signal feature is controlled by the designer and is not used automatically by the Altera software. See Altera Corporation ...

Page 22

... Global signals drive into every LAB as clock, asynchronous clear, preset, and data signals. (4) The local interconnect from LABs C22 and D22 can drive two global control signals on the right side. 22 Note (1) 4 (3) (4) LAB (Repeated LAB C22 Across Device) (4) LAB D22 Dedicated Inputs Altera Corporation ...

Page 23

... The Altera Compiler uses programmable inversion to invert the data or output enable signals automatically where appropriate. Open- drain emulation is provided by driving the data input low and toggling the OE of each IOE ...

Page 24

... IOEs are on either IOE side of a row. Each IOE can drive up to six row LAB channels, and each IOE data and OE signal is driven by IOE the local interconnect. FastFLEX I/ can drive a pin through the local interconnect for faster clock-to-output times. shows how an Altera Corporation ...

Page 25

... EPF6024A device in a 256-pin FineLine BGA package. The Altera software packages provide support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The Altera software packages generate pin-outs describing how to lay out a board to take advantage of this migration (see Altera Corporation ...

Page 26

... Designed for 256-Pin FineLine BGA Package 100-Pin FineLine BGA 256-Pin FineLine BGA Package (Reduced I/O Count or Logic Requirements) lists the 3.3-V FLEX 6000 devices with the SameFrame pin-out Device 100-Pin FineLine BGA v 256-Pin FineLine BGA (Increased I/O Count or Logic Requirements) 256-Pin FineLine BGA v v Altera Corporation ...

Page 27

... TQFP or 100-pin FineLine BGA packages. Table 7 Table 7. FLEX 6000 MultiVolt I/O Support V CCINT (V) 3.3 3.3 5.0 5.0 Note: (1) When V tolerant inputs. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet CCINT . OD1 describes FLEX 6000 MultiVolt I/O support. V Input Signal (V) CCIO (V) 2.5 3.3 5.0 v ...

Page 28

... V. When the open-drain pin is active, it will drive low. IH current specification should be considered when OL and V CCIO CCINT Table 8 See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG BST circuitry. Description = 3 5.0 V (with CCIO power planes can be powered shows JTAG instructions for Altera Corporation ...

Page 29

... The instruction register length for FLEX 6000 devices is three bits. shows the boundary-scan register length for FLEX 6000 devices. Table 9. FLEX 6000 Device Boundary-Scan Register Length FLEX 6000 devices include a weak pull-up on JTAG pins. f See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) Figure 16 Figure 16. JTAG Waveforms TMS TDI ...

Page 30

... Update register valid output to high impedance Device Output (8.06 kΩ) Device input rise and fall times < Min Max Unit 100 Figure 17. Multiple VCC 464 Ω (703 Ω) [521 Ω] To Test System 250 Ω C1 (includes [481 Ω] JIG capacitance) Altera Corporation ...

Page 31

... Output voltage O T Operating temperature J t Input rise time R t Input fall time F Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet through 18 provide information on absolute maximum ratings, Note (1) Conditions With respect to ground (2) No bias Under bias PQFP, TQFP, and BGA packages ...

Page 32

... Output capacitance OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2 overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. ...

Page 33

... I V Output voltage O T Operating temperature J t Input rise time R t Input fall time F Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Note (1) Conditions ground With respect to (2) No bias Under bias PQFP, PLCC, and BGA packages Conditions (3), (4) 3.00 (3.00) ...

Page 34

... Output capacitance OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) The minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2 overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. ...

Page 35

... Output Voltage (V) O EPF6024A 100 V CCI NT V CCI O Room Temperature 75 Typical I O Output Current (mA Output Voltage (V) O Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet shows the typical output drive characteristics of 5.0-V and 3.3-V EPF6010A EPF6016A = 3.3 V 100 = 3 Typical Output Current (mA ...

Page 36

... The Timing Analyzer provides point-to-point timing delay information, setup and hold time analysis, and device-wide performance analysis. Figure 19 routing paths to and from the various elements of the FLEX 6000 device ROW + LOCAL ) DATA_TO_REG ) SU shows the overall timing model, which maps the possible t ) REG_TO_OUT Altera Corporation ...

Page 37

... CASC_TO_REG t t LOCAL CARRY_TO_REG t DATA_TO_REG LD_CLR t CARRY_TO_CARRY t REG_TO_CARRY t DATA_TO_CARRY t t LABCARRY DIN_D t DIN_C Carry-out to Next LE in Same LAB Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet t ROW Cascade-In from Previous LE t CASC_TO_OUT t CARRY_TO_OUT t DATA_TO_OUT t t REG_TO_OUT CLR t LEGLOBAL t CARRY_TO_CASC ...

Page 38

... Cascade-in to cascade-out delay CASC_TO_CASC t Register-out to cascade-out delay REG_TO_CASC t LE input to cascade-out delay DATA_TO_CASC t LE register clock high time register clock low time CL 38 through 21 describe the FLEX 6000 internal timing Tables 22 and 23 describe FLEX 6000 external timing Note (1) Parameter Conditions Altera Corporation ...

Page 39

... different LAB Table 22. External Reference Timing Parameters Symbol t Register-to-register test pattern 1 t Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local DRR interconnects Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Note (1) Parameter = V CCIO CCINT = low voltage CCIO = V ...

Page 40

... EPF6010A and Speed Grade -2 Min Max 1.2 1.3 0.9 1.0 0.9 1.0 1.1 1.2 1.3 1.4 1.6 1.8 1.7 2.0 0.4 0.4 1.0 1.7 Conditions (8) (8) (8) Unit -3 Min Max 1.7 ns 1.2 ns 1.2 ns 1.5 ns 1.8 ns 2.3 ns 2.5 ns 0.5 ns 1.3 ns 2.1 ns Altera Corporation ...

Page 41

... Min Max t OD1 t OD2 t OD3 XZ1 t XZ2 t XZ3 t IOE IN_DELAY Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Speed Grade -2 Min Max 0.3 0.4 0.4 0.4 1.8 2.1 1.8 2.1 0.1 0.1 1.6 1.9 2.1 2.5 1.0 1.1 0.5 ...

Page 42

... Max 37.6 43.6 38.0 44.0 Speed Grade -2 Min Max 2.4 (1) 0.3 (2) 7.1 2.0 8.2 Unit -3 Min Max 1.0 ns 3.2 ns 1.4 ns 6.4 ns 6.1 ns 3.7 ns 0.9 ns 1.8 ns Unit -3 Min Max 53.7 ns 54.1 ns Unit -3 Min Max 3.3 (1) ns 0.1 (2) ns 2.0 10.1 ns Altera Corporation ...

Page 43

... DATA_TO_CASC t 4 4.0 CL Table 30. IOE Timing Microparameters for EPF6016 Devices Parameter Min t OD1 t OD2 Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet through 33 show the timing information for EPF6016 devices. Speed Grade -2 -3 Max Min 2.2 0.9 1.6 2.4 1 ...

Page 44

... Speed Grade -2 -3 Max Min 53.0 16.0 Unit Max 5.2 ns 2.8 ns 2.8 ns 5.1 ns 5.2 ns 0.6 ns 4.0 ns 5.6 ns Unit Max 1.0 ns 3.3 ns 2.5 ns 6.0 ns 6.0 ns 3.9 ns 0.5 ns 1.0 ns Unit Max 65.0 ns 20.0 ns Altera Corporation ...

Page 45

... CARRY_TO_CARRY t REG_TO_CARRY t DATA_TO_CARRY t CARRY_TO_CASC t CASC_TO_CASC t REG_TO_CASC t DATA_TO_CASC t 2 2.5 CL Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Speed Grade -2 Max Min 4.1 0.0 7.9 2.0 through 38 show the timing information for EPF6024A devices. Speed Grade -2 Min Max 1.2 1.3 ...

Page 46

... Speed Grade -2 Min Max 50.0 Unit -3 Min Max 2.5 ns 5.3 ns 9.3 ns 5.8 ns 5.8 ns 8.6 ns 12.6 ns 0.7 ns 4.4 ns 7.0 ns Unit -3 Min Max 1.1 ns 3.3 ns 3.4 ns 6.2 ns 6.1 ns 4.3 ns 0.8 ns 0.4 ns Unit -3 Min Max 60.0 ns Altera Corporation ...

Page 47

... CCACTIVE CC values are shown as I CCSTANDBY pages 31 value depends on the switching frequency and the application value, which depends on the device output load IO Application Note 74 (Evaluating Power for Altera value can be calculated with the following equation × f × N × tog × ---------------------------- - MAX LC ...

Page 48

... FPGA. Figure 20 frequency for EPF6010A, EPF6016, EPF6016A, and EPF6024A devices. 48 estimate based on typical conditions with CC should be verified during operation CC shows the relationship between the current and operating Altera Corporation ...

Page 49

... Operation f See Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000 Devices) including sample schematics, timing diagrams, configuration options, pins names, and timing parameters. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet EPF6016 1000 800 I Supply CC ...

Page 50

... Configuration Scheme Configuration device Passive serial (PS) Passive serial asynchronous (PSA) 50 shows the data sources for each configuration scheme. Data Source EPC1 or EPC1441 configuration device TM BitBlaster , ByteBlasterMV download cables, or serial data source BitBlaster, ByteBlasterMV, or MasterBlaster download cables, or serial data source MasterBlaster Altera Corporation ...

Page 51

... Device Pin- See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Outs Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet 51 ...

Page 52

... Altera, BitBlaster, ByteBlasterMV, FastFlex, FastTrack, FineLine BGA, FLEX, MasterBlaster, MAX+PLUS II, MegaCore, MultiVolt, OptiFLEX, Quartus, SameFrame, and specific device designations are trademarks and/or service marks of Altera Corporation in the United States and other countries. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog is a registered trademark of and Verilog- trademarks of Cadence Design Systems, Inc ...

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