EP2C8F256C8 Altera, EP2C8F256C8 Datasheet - Page 150
EP2C8F256C8
Manufacturer Part Number
EP2C8F256C8
Description
IC CYCLONE II FPGA 8K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8F256C8
Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
182
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1454
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8F256C8
Manufacturer:
ALTBRA
Quantity:
27
Part Number:
EP2C8F256C8
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2C8F256C8I
Manufacturer:
ALTERA
Quantity:
1 831
Company:
Part Number:
EP2C8F256C8N
Manufacturer:
ALTBRA
Quantity:
77
Company:
Part Number:
EP2C8F256C8N
Manufacturer:
ALTERA
Quantity:
672
Part Number:
EP2C8F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2C8F256C8NK
Manufacturer:
st
Quantity:
2
Timing Specifications
Figure 5–6. mini-LVDS Transmitter AC Timing Specification
Notes to
(1)
(2)
5–60
Cyclone II Device Handbook, Volume 1
Device
operation
in Mbps
t
TCCS
Output
jitter (peak
to peak)
t
t
t
D U T Y
R I S E
F A L L
L O C K
Table 5–49. Mini-LVDS Transmitter Timing Specification (Part 2 of 2)
Symbol
The data setup time, t
The data hold time, t
Figure
20–80%
80–20%
LVDSCLK[]n
LVDSCLK[]p
Conditions
5–6:
LVDS[]p
LVDS[]n
×10
×8
×7
×4
×2
×1
—
—
—
H
SU
, is 0.225 × TUI.
, is 0.225 × TUI.
In order to determine the transmitter timing requirements, mini-LVDS
receiver timing requirements on the other end of the link must be taken
into consideration. The mini-LVDS receiver timing parameters are
typically defined as t
timing parameter specifications are t
Refer to
The AC timing requirements for mini-LVDS are shown in
Min
100
80
70
40
20
10
45
—
—
—
—
—
–6 Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Figure 5–4
Max
311
311
311
311
311
311
200
500
500
500
100
55
t
SU
for the timing budget.
(1)
SU
Min
100
80
70
40
20
10
45
TUI
—
—
—
—
—
and t
–7 Speed Grade
t
H
(2)
H
Typ
—
—
—
—
—
—
—
—
—
—
—
—
requirements. Therefore, the transmitter
t
SU
CO
Max
311
311
311
311
311
311
500
500
500
100
200
55
(1)
(minimum) and t
t
Min
100
H
80
70
40
20
10
45
—
—
—
—
—
(2)
–8 Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Altera Corporation
CO
Figure
February 2008
Max
(maximum).
311
311
311
311
311
311
500
500
500
100
200
55
5–6.
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Unit
ps
ps
ps
ps
μs
%