EP20K100QC240-3 Altera, EP20K100QC240-3 Datasheet - Page 43
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EP20K100QC240-3
Manufacturer Part Number
EP20K100QC240-3
Description
IC APEX 20K FPGA 100K 240-PQFP
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K100QC240-3
Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
189
Number Of Gates
263000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1094
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K100QC240-3N
Manufacturer:
ALTERA
Quantity:
150
Part Number:
EP20K100QC240-3V
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 28. Column IOE Connection to the Interconnect
Altera Corporation
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
Row Interconnect
Figure 28
Dedicated Fast I/O Pins
APEX 20KE devices incorporate an enhancement to support bidirectional
pins with high internal fanout such as PCI control signals. These pins are
called Dedicated Fast I/O pins (FAST1, FAST2, FAST3, and FAST4) and
replace dedicated inputs. These pins can be used for fast clock, clear, or
high fanout logic signal distribution. They also can drive out. The
Dedicated Fast I/O pin data output and tri-state control are driven by
local interconnect from the adjacent MegaLAB for high speed.
Each IOE can drive column interconnect. In APEX 20KE devices,
IOEs can also drive FastRow interconnect. Each IOE data
and OE signal is driven by local interconnect.
IOE
shows how a column IOE connects to the interconnect.
MegaLAB Interconnect
APEX 20K Programmable Logic Device Family Data Sheet
LAB
IOE
Column Interconnect
43