EPF10K30RI208-4 Altera, EPF10K30RI208-4 Datasheet - Page 41
Manufacturer Part Number
IC FLEX 10K FPGA 30K 208-RQFP
Specifications of EPF10K30RI208-4
Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Number Of Gates
Voltage - Supply
4.5 V ~ 5.5 V
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 13. FLEX 10K JTAG Instructions
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
Selects the user electronic signature (USERCODE) register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO.
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.
These instructions are used when configuring a FLEX 10K device via JTAG ports with a
BitBlaster, or ByteBlasterMV or MasterBlaster download cable, or using a Jam File
(.jam) or Jam Byte-Code File (.jbc) via an embedded processor.
The instruction register length of FLEX 10K devices is 10 bits. The
USERCODE register length in FLEX 10K devices is 32 bits; 7 bits are
determined by the user, and 25 bits are predetermined.
show the boundary-scan register length and device IDCODE information
for FLEX 10K devices.
Table 14. FLEX 10K Boundary-Scan Register Length
FLEX 10K Embedded Programmable Logic Device Family Data Sheet