EP1S10F780C7 Altera, EP1S10F780C7 Datasheet - Page 83

IC STRATIX FPGA 10K LE 780-FBGA

EP1S10F780C7

Manufacturer Part Number
EP1S10F780C7
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S10F780C7

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
426
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1112

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S10F780C7
Manufacturer:
EUTECH
Quantity:
3 930
Part Number:
EP1S10F780C7
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S10F780C7
Manufacturer:
ALTERA
0
Part Number:
EP1S10F780C7
Manufacturer:
ALTERA
Quantity:
50
Part Number:
EP1S10F780C7ES
Manufacturer:
ALTERA
Quantity:
44
Part Number:
EP1S10F780C7ES
Manufacturer:
ALTERA
Quantity:
89
Part Number:
EP1S10F780C7ES
Manufacturer:
ALTERA
0
Part Number:
EP1S10F780C7L
Manufacturer:
ALTERA
Quantity:
17
Part Number:
EP1S10F780C7L
Manufacturer:
ALTERA
0
Part Number:
EP1S10F780C7N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F780C7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S10F780C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–39. Four-Multipliers Adder Mode
Notes to
(1)
(2)
Altera Corporation
July 2005
These signals are not registered or registered once to match the data path pipeline.
These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
Data B
Data B
Data B
Data B
Data A
Data A
Data A
Data A
Figure
shiftout B
2–39:
shiftin B
shiftout A
ENA
ENA
ENA
ENA
ENA
ENA
ENA
ENA
D
D
D
D
D
D
D
D
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
shiftin A
Q
Q
Q
Q
Q
Q
Q
Q
signa (1)
signb (1)
clock
aclr
ena
ENA
ENA
ENA
ENA
D
D
D
D
CLRN
CLRN
CLRN
CLRN
Q
Q
Q
Q
addnsub1 (2)
addnsub3 (2)
signa (2)
signb (2)
Adder/Subtractor
Adder/Subtractor
Stratix Device Handbook, Volume 1
Summation
D
ENA
CLRN
Stratix Architecture
Q
Data Out
2–69

Related parts for EP1S10F780C7