EP3C120F780C8 Altera, EP3C120F780C8 Datasheet - Page 16
![IC CYCLONE III FPGA 119K 780FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP3C120F780C8
Manufacturer Part Number
EP3C120F780C8
Description
IC CYCLONE III FPGA 119K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
Specifications of EP3C120F780C8
Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
531
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2391
544-2531
544-2531
EP3C120F780C8ES
544-2531
544-2531
EP3C120F780C8ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C120F780C8
Manufacturer:
ALTERA
Quantity:
561
Company:
Part Number:
EP3C120F780C8N
Manufacturer:
ALTERA
Quantity:
642
Part Number:
EP3C120F780C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 16
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The Logic Analyzer Interface requires JTAG connection and communicates with the
device through an Altera download cable. Additional LEs and I/Os are needed as
well.
For more information about ways to use the Logic Analyzer Interface feature for
debugging, refer to the
volume 3 of the Quartus II Handbook.
In-System Memory Content Editor
The In-System Memory Content Editor feature allows you to modify the content of
the memory or constant through the JTAG interface. This is useful in debugging for
design examples that perform read and write operation on the memory so that you
can check whether the design writes or reads the correct data to or from the memory.
Changes to the memory or constant can be done without interrupting the device's
functionality.
Specify that the memory or constant are modifiable when instantiating the
megafunction for the memory or constant. The In-System Memory Content Editor
requires JTAG connection and communicates with the device through an Altera
download cable. Additional LEs are needed when this feature is turned on.
For more information on ways to use the In-System Memory Content Editor to access
the on-chip memory, refer to the
in volume 3 of the Quartus II Handbook.
In-System Sources and Probes
This feature allows you to input simple virtual stimuli and capture the current value
of internal nodes in your design dynamically without the use of any external test
equipment. You can force trigger conditions set up using the SignalTap II Logic
Analyzer. The feature needs the altsource_probe megafunction instantiated in your
design before compilation and requires JTAG connection for the communication
through an Altera download cable. Additional LEs are needed when this feature is
used.
For more information on ways to use the In-System Source and Probes for debugging,
refer to the
the Quartus II Handbook.
Virtual JTAG Megafunction
Similar to the in-System Sources and Probes, the Virtual JTAG megafunction allows
you to apply virtual stimuli and capture the current value of internal nodes in your
design dynamically without the use of any external test equipment, albeit the Virtual
JTAG megafunction gives you a greater level of control but at the cost of greater
complexity. The feature needs the sld_virtual_jtag megafunction instantiated in your
design before compilation and requires JTAG connection for the communication
through an Altera download cable. Additional LEs are needed when this feature is
used.
For more information on ways to use the sld_virtual_jtag megafunction for
debugging, refer to the
Design Debugging Using In-System Sources and Probes
In-System Debugging Using External Logic Analyzers
sld_virtual_jtag Megafunction User
In-System Updating of Memory and Constants
Guide.
© November 2008 Altera Corporation
chapter in volume 3 of
Early System Planning
chapter in
chapter