EP2S30F484C5 Altera, EP2S30F484C5 Datasheet - Page 50

• Manufacturer Part Number: EP2S30F484C5
• Description: IC STRATIX II FPGA 30K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S30F484C5

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 342
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1107

Digital Signal Processing Block
2–42
Stratix II Device Handbook, Volume 1
Table 2–5
DSP block multipliers can optionally feed an adder/subtractor or
accumulator in the block depending on the configuration. This makes
routing to ALMs easier, saves ALM routing resources, and increases
performance, because all connections and blocks are in the DSP block.
Additionally, the DSP block input registers can efficiently implement shift
registers for FIR filter applications, and DSP blocks support Q1.15 format
rounding and saturation.
Figure 2–28
18 × 18-bit multiplier mode.
Note to
(1)
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
Table 2–5. DSP Blocks in Stratix II Devices
Device
Each device has either the numbers of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
Table
shows the number of DSP blocks in each Stratix II device.
shows the top-level diagram of the DSP block configured for
DSP Blocks
2–5:
12
16
36
48
63
96
Multipliers
Total 9 × 9
128
288
384
504
768
96
Note (1)
Total 18 × 18
Multipliers
144
192
252
384
48
64
Altera Corporation
Total 36 × 36
Multipliers
May 2007
12
16
36
48
63
96