EP1AGX90EF1152C6N Altera, EP1AGX90EF1152C6N Datasheet - Page 106

• Manufacturer Part Number: EP1AGX90EF1152C6N
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152C6N

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2379

2–100
Table 2–30. EP1AGX20 Device Differential Channels
Table 2–31. EP1AGX35 Device Differential Channels
Arria GX Device Handbook, Volume 1
Note to
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
484-pin FineLine BGA
780-pin FineLine BGA
Note to
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
484-pin FineLine BGA
780-pin FineLine GBA
Package
Package
Table
Table
2–30:
2–31:
1
device, PLL 1 can drive a maximum of 16 transmitter channels in I/O Bank 2 or a
maximum of 29 transmitter channels in I/O Banks 1 and 2. The Quartus II software
can also merge receiver and transmitter PLLs when a receiver is driving a transmitter.
In this case, one fast PLL can drive both the maximum numbers of receiver and
transmitter channels.
For more information, refer to the “Differential Pin Placement Guidelines” section in
the
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter/Receiver
Transmitter/Receiver
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
(Note 1)
Total Channels
Total Channels
(Note 1)
29
31
29
31
29
31
29
31
PLL1
PLL1
16
13
17
14
16
13
17
14
16
13
17
14
16
13
17
14
High-Speed Differential I/O with DPA Support
Center Fast PLLs
Center Fast PLLs
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
chapter.
PLL2
PLL2
13
16
14
17
13
16
14
17
13
16
14
17
13
16
14
17