EP2S60F672C5N Altera, EP2S60F672C5N Datasheet - Page 133
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EP2S60F672C5N
Manufacturer Part Number
EP2S60F672C5N
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C5N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
492
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1914
EP2S60F672C5N
EP2S60F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Hot Socketing
Feature
Implementation
in Stratix II
Devices
Altera Corporation
May 2007
I
takes into account the pin capacitance, but not board trace and external
loading capacitance. Additional capacitance for trace, connector, and
loading needs must be considered separately. For the AC specification,
the peak current duration is 10 ns or less because of power-up transients.
For more information, refer to the Hot-Socketing & Power-Sequencing
Feature & Testing for Altera Devices white paper.
A possible concern regarding hot-socketing is the potential for latch-up.
Latch-up can occur when electrical subsystems are hot-socketed into an
active system. During hot-socketing, the signal pins may be connected
and driven by the active system before the power supply can provide
current to the device's V
latch-up and cause a low-impedance path from V
device. As a result, the device extends a large amount of current, possibly
causing electrical damage. Nevertheless, Stratix II devices are immune to
latch-up when hot-socketing.
The hot socketing feature turns off the output buffer during the power-up
event (either V
socket circuit will generate an internal HOTSCKT signal when either
V
will cut off the output buffer to make sure that no DC current (except for
weak pull up leaking) leaks through the pin. When V
slowly, V
the configuration is finished. The CONF_DONE, nCEO, and nSTATUS pins
fail to respond, as the output buffer can not flip from the state set by the
hot socketing circuit at this low V
circuit has been removed on these configuration pins to make sure that
they are able to operate during configuration. It is expected behavior for
these pins to drive out during power-up and power-down sequences.
Each I/O pin has the following circuitry shown in
IOPIN
CCINT
is the current at any user I/O pin on the device. This specification
, V
CC
CCIO
is still relatively low even after the POR signal is released and
, or V
CCINT
CCPD
, V
CCIO
is below threshold voltage. The HOTSCKT signal
CC
, or V
and ground planes. This condition can lead to
CCPD
CC
voltage. Therefore, the hot socketing
supplies) or power down. The hot-
Stratix II Device Handbook, Volume 1
Hot Socketing & Power-On Reset
CC
Figure
to ground within the
CC
ramps up very
4–1.
4–3