XC3S50AN-4TQG144C Xilinx Inc, XC3S50AN-4TQG144C Datasheet - Page 65
![IC SPARTAN-3AN FPGA 50K 144TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S50AN-4TQG144C
Manufacturer Part Number
XC3S50AN-4TQG144C
Description
IC SPARTAN-3AN FPGA 50K 144TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S50AN-4TQG144C
Total Ram Bits
55296
Number Of Logic Elements/cells
1584
Number Of Labs/clbs
176
Number Of I /o
108
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
No. Of Logic Blocks
1584
No. Of Gates
50000
No. Of Macrocells
1584
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
108
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1555
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S50AN-4TQG144C
Manufacturer:
TOSHIBA
Quantity:
1 000
Company:
Part Number:
XC3S50AN-4TQG144C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S50AN-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
External Serial Peripheral Interface (SPI) Configuration Timing
X-Ref Target - Figure 16
Table 57: Timing for External Serial Peripheral Interface (SPI) Configuration Mode
DS557 (v4.1) April 1, 2011
Product Specification
(Open-Drain)
T
T
T
T
T
T
T
PROG_B
CCLK1
CCLKn
MINIT
INITM
CCO
DCC
CCD
PUDC_B
Symbol
VS[2:0]
CSO_B
INIT_B
M[2:0]
CCLK
(Input)
(Input)
(Input)
(Input)
(Input)
MOSI
DIN
Shaded values indicate specifications on attached SPI Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate bitstream option setting
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B
MOSI output valid delay after CCLK falling clock edge
Setup time on the DIN data input before CCLK rising clock edge
Hold time on the DIN data input after CCLK rising clock edge
Figure 16: Waveforms for External Serial Peripheral Interface (SPI) Configuration
T
MINIT
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
<1:1:1>
<0:0:1>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
T
CCLK1
Description
T
CSS
Command
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
(msb)
T
CCO
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
T
DSU
T
MCCL1
Command
(msb-1)
T
MCCH1
T
DH
Minimum
Data
50
0
T
T
New ConfigRate active
CCLK1
See
See
See
See
See
MCCL n
Data
T
T
Maximum
V
DCC
Table 51
Table 51
Table 55
Table 55
Table 55
–
–
Data
DS529-3_06_102506
T
T
CCLK n
T
CCD
MCCH n
Units
ns
ns
Data
65