XC3S200-4PQG208C Xilinx Inc, XC3S200-4PQG208C Datasheet - Page 82

• Manufacturer Part Number: XC3S200-4PQG208C
• Description: IC SPARTAN-3 FPGA 200K 208-PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4PQG208C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 4320
• Number Of Labs/clbs: 480
• Number Of I /o: 141
• Number Of Gates: 200000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• No. Of Logic Blocks: 480
• No. Of Gates: 200000
• No. Of Macrocells: 4320
• Family Type: Spartan-3
• No. Of Speed Grades: 4
• No. Of I/o's: 141
• Clock: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1339

Spartan-3 FPGA Family: DC and Switching Characteristics
Internal Logic Timing
Table 50: CLB Timing
82
Notes:
1.
2.
3.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
F
Propagation Times
T
Set/Reset Pulse Width
T
AS
AH
CKO
DICK
CKDI
CH
CL
TOG
ILO
RPW_CLB
The numbers in this table are based on the operating conditions set forth in
The timing shown is for SLICEM.
For minimums, use the values reported by the Xilinx timing analyzer.
Symbol
When reading from the FFX (FFY) Flip-Flop,
the time from the active transition at the CLK
input to data appearing at the XQ (YQ) output
Time from the setup of data at the F or G input
to the active transition at the CLK input of the
CLB
Time from the setup of data at the BX or BY
input to the active transition at the CLK input of
the CLB
Time from the active transition at the CLK input
to the point where data is last held at the F or
G input
Time from the active transition at the CLK input
to the point where data is last held at the BX or
BY input
CLB CLK signal High pulse width
CLB CLK signal Low pulse width
Maximum toggle frequency (for export control)
The time it takes for data to travel from the
CLB’s F (G) input to the X (Y) output
The minimum allowable pulse width, High or
Low, to the CLB’s SR input
Description
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0.46
1.27
0.25
0.69
0.76
0.69
Min
0
Table
-
-
-
-5
31.
Max
0.63
0.53
725
Speed Grade
∞
∞
-
-
-
-
-
DS099-3 (v2.5) December 4, 2009
0.53
1.57
0.29
0.79
0.79
0.87
Min
0
-
-
-
-4
Product Specification
Max
0.72
0.61
630
∞
∞
-
-
-
-
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
R