XC3S1200E-4FGG400C Xilinx Inc, XC3S1200E-4FGG400C Datasheet - Page 17
![IC SPARTAN-3E FPGA 1200K 400FBGA](/photos/6/72/67298/pk083-400_sml.jpg)
XC3S1200E-4FGG400C
Manufacturer Part Number
XC3S1200E-4FGG400C
Description
IC SPARTAN-3E FPGA 1200K 400FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1200E-4FGG400C
Total Ram Bits
516096
Number Of Logic Elements/cells
19512
Number Of Labs/clbs
2168
Number Of I /o
304
Number Of Gates
1200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
400-BGA
No. Of Logic Blocks
19512
No. Of Gates
1200000
No. Of Macrocells
19512
No. Of Speed Grades
4
No. Of I/o's
304
Clock Management
DLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1480
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
XC3S1200E-4FGG400C
Manufacturer:
XILINX
Quantity:
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Part Number:
XC3S1200E-4FGG400C
Manufacturer:
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Table 6: Single-Ended IOSTANDARD Bank Compatibility (Continued)
Table 7: Differential IOSTANDARD Bank Compatibility
HSTL and SSTL inputs use the Reference Voltage (V
bias the input-switching threshold. Once a configuration
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use HSTL/SSTL, a few specifically reserved
I/O pins on the same bank automatically convert to V
inputs. For banks that do not contain HSTL or SSTL, V
pins remain available for user I/Os or input pins.
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling proper-
ties (for example, Common-Mode Rejection) of these stan-
dards permit exceptionally high data transfer rates. This
DS312-2 (v3.8) August 26, 2009
Product Specification
Notes:
1.
Notes:
1.
SSTL18_I
SSTL2_I
LVDS_25
RSDS_25
MINI_LVDS_25
LVPECL_25
BLVDS_25
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
IOSTANDARD
Single-Ended
IOSTANDARD
N/R - Not required for input operation.
Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.
Differential
R
1.2V
Output
Output
Output
Input,
Input,
Input,
-
-
Input
Input
Input
Input
Input
Input
1.8V
1.5V
On-chip Differential Termination,
On-chip Differential Termination,
On-chip Differential Termination,
V
CCO
-
-
Supply/Compatibility
V
CCO
Output
Input/
1.8V
Output
Output
Output
Output
Output
Input,
Input,
Input,
Input,
Input,
Input
Input
Input
Input
2.5V
-
Supply
REF
www.xilinx.com
REF
REF
) to
Output
Input/
Input
2.5V
subsection introduces the differential signaling capabilities
of Spartan-3E devices.
Each device-package combination designates specific I/O
pairs specially optimized to support differential standards. A
unique L-number, part of the pin name, identifies the
line-pairs associated with each bank (see
tions
nate the true and inverted lines, respectively. For example,
the pin names IO_L43P_3 and IO_L43N_3 indicate the true
and inverted lines comprising the line pair L43 on Bank 3.
in Module 4). For each pair, the letters P and N desig-
Input
Input
3.3V
Input
Input
Input
Input
Input
Input
Input
Input
Input
3.3V
V
Requirements:
REF
for these I/O
standards
V
1.25
is not used
Input
V
0.9
REF
Input Requirements
REF
Functional Description
restrictions might
Bank Restriction
Differential Bank
(other I/O bank
Voltage (V
Pinout Descrip-
No Differential
Termination
Outputs Only
Outputs Only
Outputs Only
Restriction
Applies to
Applies to
Applies to
Board
apply)
1.25
0.9
TT
(1)
)
17