XC5VLX30T-1FFG665C Xilinx Inc, XC5VLX30T-1FFG665C Datasheet - Page 66
XC5VLX30T-1FFG665C
Manufacturer Part Number
XC5VLX30T-1FFG665C
Description
IC FPGA VIRTEX-5 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665C
Total Ram Bits
1327104
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
No. Of Logic Blocks
4800
No. Of Gates
30000
No. Of Macrocells
4800
No. Of Speed Grades
1
No. Of I/o's
360
Clock Management
PLL
Dc
1045
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1560
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX30T-1FFG665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX30T-1FFG665C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Company:
Part Number:
XC5VLX30T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 66 of 385
- Download datasheet (14Mb)
Chapter 2: Clock Management Technology
X-Ref Target - Figure 2-4
66
Source
CLK
IBUFG
System-Synchronous
This delay element allows adjustment of the effective clock delay between the clock source
and CLK0 to guarantee non-positive hold times of IOB input flip-flop in the device.
Adding more delay to the DCM feedback path decreases the effective delay of the actual
clock path from the FPGA clock input pin to the clock input of any flip-flop. Decreasing the
clock delay increases the setup time represented in the input flip-flop, and reduces any
positive hold times required. The clock path delay includes the delay through the IBUFG,
route, DCM, BUFG, and clock-tree to the destination flip-flop. If the feedback delay equals
the clock-path delay, the effective clock-path delay is zero.
System-Synchronous Setting (Default)
By default, the feedback delay is set to system-synchronous mode. The primary timing
requirements for a system-synchronous system are non-positive hold times (or minimally
positive hold times) and minimal clock-to-out and setup times. Faster clock-to-out and
setup times allow shorter system clock periods. Ideally, the purpose of a DLL is to zero-out
the clock delay to produce faster clock-to-out and non-positive hold times. The system-
synchronous setting (default) for DESKEW_ADJUST configures the feedback delay
element to guarantee non-positive hold times for all input IOB registers. The exact delay
number added to the feedback path is device size dependent. This is determined by
characterization. In the timing report, this is included as timing reduction to input clock
path represented by the T
includes tap delays in the default setting (red line). The pin-to-pin timing parameters (with
DCM) on the Virtex-5 FPGA Data Sheet reflects the setup/hold and clock-to-out times when
the DCM is in system-synchronous mode.
In some situations, the DCM does not add this extra feedback delay, and the
DESKEW_ADJUST parameter has no effect. BitGen selects the appropriate DCM Tap
settings. These situations include:
Default Setting
Figure 2-4: DCM and Feedback Tap-Delay Elements
DCM
Feedback Tap Delays
…
Setting (Delay set to zero)
CLKIN
CLKFB
Source-Synchronous
DCMINO
www.xilinx.com
CLK0
Data Input
parameter. As shown in
Regulator
V
Power
DCM
CCINT
V
CCO
Figure
D
FF
Q
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
2-4, the feedback path
ug190_2_04_042506
Into the
V
FPGA
CCAUX
Related parts for XC5VLX30T-1FFG665C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IC FPGA VIRTEX-5LX 30K 665-FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
FPGA Virtex®-5 Family 30720 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
FPGA Virtex®-5 Family 30720 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
FPGA Virtex®-5 Family 30720 Cells 65nm (CMOS) Technology 1V 323-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
FPGA Virtex®-5 Family 30720 Cells 65nm (CMOS) Technology 1V 323-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
FPGA Virtex®-5 Family 30720 Cells 65nm (CMOS) Technology 1V 323-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5LX 30K 665-FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5LX 30K 323-FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5LX 30K 665-FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5LX 30K 665-FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5LXT 323FFBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5LXT 665FFBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5LX 30K 323-FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX 5 30K 323FFGBGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer:
Xilinx Inc
Datasheet: