XC5VSX35T-1FFG665C Xilinx Inc, XC5VSX35T-1FFG665C Datasheet - Page 134

• Manufacturer Part Number: XC5VSX35T-1FFG665C
• Description: IC FPGA VIRTEX-5 35K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX35T-1FFG665C

• Total Ram Bits: 3096576
• Number Of Logic Elements/cells: 34816
• Number Of Labs/clbs: 2720
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• No. Of Logic Blocks: 5440
• No. Of Gates: 35000
• Family Type: Virtex-5 SXT
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1566

Chapter 4: Block RAM
X-Ref Target - Figure 4-12
X-Ref Target - Figure 4-13
Block RAM Timing Model
134
RAMEN
DBRAM
RAMEN
DBRAM
REGCE
REGCE
SSR
SSR
CLK
CLK
SSR only sets/resets DO when REGCE is also High.
DO
DO
Figure 4-13: SSR Operation in Register Mode with Variable REGCE
Figure 4-12: SSR Operation in Register Mode with REGCE High
This section describes the timing parameters associated with the block RAM in Virtex-5
devices (illustrated in
FPGA Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software are also
available for reference.
D0
D0
Block RAM can be read when SSR is active.
D0
D0
Data appears on the output of the next REGCE.
Figure
www.xilinx.com
SRVAL
SRVAL
D1
D1
4-14). The switching characteristics section in the Virtex-5
D1
D1
SRVAL
D2
D2
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_4_29_071607
ug190_4_29_071607
D2
D3
D3
D2