AT40K10-2AJI Atmel, AT40K10-2AJI Datasheet - Page 27

• Manufacturer Part Number: AT40K10-2AJI
• Description: IC FPGA 10K GATES 84PLCC
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K10-2AJI

• Number Of Logic Elements/cells: 576
• Total Ram Bits: 4608
• Number Of I /o: 62
• Number Of Gates: 20000
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -
• Other names: AT40K102AJI

AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
Minimum times based on best case: V
Maximum delays are the average of t
Clocks and Reset Input buffers are measured from a V
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
0896C–FPGA–04/02
Cell Function
Global Clocks and Set/Reset
GCLK Input Buffer
FCLK Input Buffer
Clock Column Driver
Clock Sector Driver
GSRN Input Buffer
Global Clock to Output
Fast Clock to Output
Parameter
t
t
t
t
t
t
t
PD
PD
PD
PD
PD
PD
PD
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
PDLH
CC
CC
= 5.25V, temperature = 0°C
and t
= 4.75V, temperature = 70°C
Path
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
clock -> colclk
clock -> colclk
clock -> colclk
clock -> colclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
pad -> GSRN
pad -> GSRN
pad -> GSRN
pad -> GSRN
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
PDHL
.
IH
of 1.5V at the input pad to the internal V
AT40K/AT40KLV Series FPGA
Device
AT40K05
AT40K10
AT40K20
AT40K40
AT40K05
AT40K10
AT40K20
AT40K40
AT40K05
AT40K10
AT40K20
AT40K40
AT40K05
AT40K10
AT40K20
AT40K40
AT40K05
AT40K10
AT40K20
AT40K40
AT40K05
AT40K10
AT40K20
AT40K40
AT40K05
AT40K10
AT40K20
AT40K40
1.1
1.2
1.2
1.4
0.7
0.8
0.8
0.8
0.8
0.9
1.0
1.1
0.5
0.5
0.5
0.5
3.0
3.7
4.3
5.6
8.3
8.4
8.6
8.8
7.9
8.0
8.1
8.3
-2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IH
of 50% of V
Notes
Rising edge clock
Rising edge clock
Rising edge clock
Rising edge clock
From any pad to Global
Set/Reset network
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
CC
.
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