AT40K20-2EQC Atmel, AT40K20-2EQC Datasheet - Page 59

IC FPGA 20K GATES 240PQFP

AT40K20-2EQC

Manufacturer Part Number
AT40K20-2EQC
Description
IC FPGA 20K GATES 240PQFP
Manufacturer
Atmel
Series
AT40K/KLVr
Datasheets

Specifications of AT40K20-2EQC

Number Of Logic Elements/cells
1024
Total Ram Bits
8192
Number Of I /o
193
Number Of Gates
30000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
240-BFQFP
Family Name
AT40K
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1024
# Registers
1024
# I/os (max)
193
Process Technology
0.6um (CMOS)
Operating Supply Voltage (typ)
5V
Logic Cells
1024
Ram Bits
8192
Device System Gates
30000
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Labs/clbs
-
Lead Free Status / Rohs Status
Not Compliant
Other names
AT40K202EQC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT40K20-2EQC
Manufacturer:
Atmel
Quantity:
10 000
100T1 – TQFP
0896C–FPGA–04/02
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating place to the lowest point on the package body.
e
datums, etc.
body size dimensions, including mold mismatch.
b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and
an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages.
R
A1
2325 Orchard Parkway
San Jose, CA 95131
b
A2
Top View
Side View
L1
D1
TITLE
100T1, 100-lead (14 x 14 x 1.0 mm Body), Thin Plastic
Quad Flat Pack (TQFP)
E1
AT40K/AT40KLV Series FPGA
SYMBOL
XX
A1
A2
D
D1
E
E1
e
b
L1
Bottom View
0.05
0.95
0.17
COMMON DIMENSIONS
MIN
(Unit of Measure = mm)
D
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
0.50 BSC
1.00 REF
NOM
1.00
0.22
N
DRAWING NO.
0.15
1.05
0.27
100T1
MAX
NOTE
E
6
2, 3
2, 3
4, 5
11/30/01
REV.
A
59

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