EP3C10F256C8 Altera, EP3C10F256C8 Datasheet - Page 8

• Manufacturer Part Number: EP3C10F256C8
• Description: IC CYCLONE III FPGA 10K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C10F256C8

• Number Of Logic Elements/cells: 10320
• Number Of Labs/clbs: 645
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2416; EP3C10F256C8

1–8
I/O Features
High-Speed Differential Interfaces
Auto-Calibrating External Memory Interfaces
Cyclone III Device Handbook, Volume 1
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Cyclone III device family has eight I/O banks. All I/O banks support single-ended
and differential I/O standards listed in
Table 1–6. Cyclone III Device Family I/O Standards Support
The Cyclone III device family I/O also supports programmable bus hold,
programmable pull-up resistors, programmable delay, programmable drive strength,
programmable slew-rate control to optimize signal integrity, and hot socketing.
Cyclone III device family supports calibrated on-chip series termination (R
driver impedance matching (Rs) for single-ended I/O standards, with one OCT
calibration block per side.
For more information, refer to the
Cyclone III device family supports high-speed differential interfaces such as BLVDS,
LVDS, mini-LVDS, RSDS, and PPDS. These high-speed I/O standards in Cyclone III
device family provide high data throughput using a relatively small number of I/O
pins and are ideal for low-cost applications. Dedicated differential output drivers on
the left and right I/O banks can send data rates at up to 875 Mbps for Cyclone III
devices and up to 740 Mbps for Cyclone III LS devices, without the need for external
resistors. This saves board space or simplifies PCB routing. Top and bottom I/O banks
support differential transmission (with the addition of an external resistor network)
data rates at up to 640 Mbps for both Cyclone III and Cyclone III LS devices.
For more information, refer to the
chapter.
Cyclone III device family supports common memory types such as DDR, DDR2,
SDR SDRAM, and QDRII SRAM. DDR2 SDRAM memory interfaces support data
rates up to 400 Mbps for Cyclone III devices and 333 Mbps for Cyclone III LS devices.
Memory interfaces are supported on all sides of Cyclone III device family. Cyclone III
device family has the OCT, DDR output registers, and 8-to-36-bit programmable DQ
group widths features to enable rapid and robust implementation of different
memory standards.
An auto-calibrating megafunction is available in the Quartus II software for DDR and
QDR memory interface PHYs. This megafunction is optimized to take advantage of
the Cyclone III device family I/O structure, simplify timing closure requirements, and
take advantage of the Cyclone III device family PLL dynamic reconfiguration feature
to calibrate PVT changes.
For more information, refer to the
chapter.
Single-Ended I/O
Differential I/O
Type
LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X
SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS
High-Speed Differential Interfaces in Cyclone III Devices
Cyclone III Device I/O Features
External Memory Interfaces in Cyclone III Devices
Table
1–6.
I/O Standard
Chapter 1: Cyclone III Device Family Overview
© December 2009 Altera Corporation
Cyclone III Device Family Architecture
chapter.
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