EP3C25Q240C8N Altera, EP3C25Q240C8N Datasheet - Page 53

IC CYCLONE III FPGA 25K 240-PQFP

EP3C25Q240C8N

Manufacturer Part Number
EP3C25Q240C8N
Description
IC CYCLONE III FPGA 25K 240-PQFP
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C25Q240C8N

Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
148
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2076
EP3C25Q240C8NES

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Verification
Figure 13. Specifying the Number of Processors
© November 2008 Altera Corporation
f
Preserving Performance
You can use the incremental compilation feature to preserve unchanged parts of your
design, thus preserving performance and allowing you to reach timing closure more
efficiently. For guidelines and references, refer to
Team-Based Design” on page
Reducing Compilation Time
You can speed up design iteration time by an average of 60% when making changes to
the design with the incremental compilation feature.
For guidelines and references, refer to the
Design” on page
The Quartus II software can run some algorithms in parallel to take advantage of
multiple processors and reduce compilation time when more than one processor is
available to compile the design. To set the number of processors available for a
Quartus II compilation, specify the Maximum processors allows for parallel
compilation on the Compilation Process Settings page of the Settings dialog box, as
in
parallel compilation.
Figure
13. The default value for the number of processors is 1, which disables
35.
35.
“Planning for Hierarchical and Team-Based
“Planning for Hierarchical and
Page 53

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