EP2C20F256I8N Altera, EP2C20F256I8N Datasheet - Page 160
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EP2C20F256I8N
Manufacturer Part Number
EP2C20F256I8N
Description
IC CYCLONE II FPGA 20K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C20F256I8N
Number Of Logic Elements/cells
18752
Number Of Labs/clbs
1172
Total Ram Bits
239616
Number Of I /o
152
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
18752
# I/os (max)
152
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
18752
Ram Bits
239616
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2103
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C20F256I8N
Manufacturer:
ALTERA
Quantity:
319
Part Number:
EP2C20F256I8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Duty Cycle Distortion
5–70
Cyclone II Device Handbook, Volume 1
Here is an example for calculating the DCD as a percentage for an SDR
output on a row I/O on a –6 device:
If the SDR output I/O standard is SSTL-2 Class II, the maximum DCD is
65 ps (refer to
period T is:
To calculate the DCD as a percentage:
Notes to
(1)
(2)
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential HSTL-18 Class I
Differential HSTL-15 Class I
LVDS
Simple RSDS
Mini LVDS
PCI
PCI-X
LVCMOS
LVTTL
Table 5–55. Maximum DCD for Single Data Outputs (SDR) on Row I/O
Pins
Table 5–56. Maximum DCD for SDR Output on Column I/O
(Part 1 of 2)
Column I/O Output Standard
T = 1/ f = 1 / 167 MHz = 6 ns = 6000 ps
(T/2 – DCD) / T = (6000 ps/2 – 65 ps) / 6000 ps = 48.91% (for low
boundary)
(T/2 + DCD) / T = (6000 ps/2 + 65 ps) / 6000ps = 51.08% (for high
boundary
Row I/O Output Standard
The DCD specification is characterized using the maximum drive strength
available for each I/O standard.
Numbers are applicable for commercial, industrial, and automotive devices.
Notes
Table
(1),
5–55:
Table
(2)
5–55). If the clock frequency is 167 MHz, the clock
(Part 2 of 2)
145
195
195
C6
60
65
90
85
60
60
60
195
210
C6
165
155
145
255
255
C7
60
60
60
90
75
285
305
C7
Altera Corporation
165
155
205
255
255
Notes
C8
90
75
60
60
60
285
305
C8
February 2008
(1),
Unit
(2)
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps