EPF10K30AQC240-3N Altera, EPF10K30AQC240-3N Datasheet - Page 24
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EPF10K30AQC240-3N
Manufacturer Part Number
EPF10K30AQC240-3N
Description
IC FLEX 10KA FPGA 30K 240-PQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K30AQC240-3N
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
12288
Number Of I /o
189
Number Of Gates
69000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KA
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# I/os (max)
189
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
3.3V
Logic Cells
1728
Ram Bits
12288
Device System Gates
69000
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1941
EPF10K30AQC240-3N
EPF10K30AQC240-3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K30AQC240-3N
Manufacturer:
ALTERA
Quantity:
20 000
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load,
or with an asynchronous clear. If DATA3 is tied to V
, asserting
CC
LABCTRL1 asynchronously loads a one into the register. Alternatively, the
Altera software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used for one of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. DATA3 is tied to V
,
CC
therefore, asserting LABCTRL1 asynchronously loads a one into the
register, effectively presetting the register. Asserting LABCTRL2 clears the
register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear. LABCTRL2 implements the clear by
controlling the register clear; LABCTRL2 does not have to feed the preset
circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear.
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Altera Corporation