EP2S30F484C5N Altera, EP2S30F484C5N Datasheet - Page 51
EP2S30F484C5N
Manufacturer Part Number
EP2S30F484C5N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
342
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
342
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
484
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1892
EP2S30F484C5N
EP2S30F484C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F484C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–28. DSP Block Diagram for 18 × 18-Bit Configuration
Altera Corporation
May 2007
Optional Serial Shift
Register Outputs to
interface block
Next DSP Block
in the Column
From the row
Register Inputs from
Optional Serial Shift
Previous DSP Block
PRN
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
PRN
PRN
PRN
PRN
PRN
PRN
PRN
Q
Q
Q
Q
Q
Q
Q
Q
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
Saturate
Saturate
Saturate
Saturate
Round/
Round/
Round/
Round/
Q1.15
Q1.15
Q1.15
Q1.15
Multiplier Block
D
ENA
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
CLRN
PRN
PRN
PRN
PRN
Q
Q
Q
Q
Adder Output Block
Optional Pipline
Register Stage
Accumulator
Accumulator
Optional Stage Configurable
as Accumulator or Dynamic
Subtractor/
Subtractor/
Adder/
Adder/
2
1
Adder/Subtractor
Stratix II Device Handbook, Volume 1
Saturate
Saturate
Multipliers Together
Round/
Round/
Q1.15
Q1.15
Summation Stage
for Adding Four
Summation
Block
Adder
Interconnect
to MultiTrack
Multiplexer
Selection
Output
Stratix II Architecture
ENA
D
CLRN
Q
2–43