EP2S30F672I4N Altera, EP2S30F672I4N Datasheet - Page 70

IC STRATIX II FPGA 30K 672-FBGA

EP2S30F672I4N

Manufacturer Part Number
EP2S30F672I4N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S30F672I4N

Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1900
EP2S30F672I4N

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PLLs & Clock Networks
2–62
Stratix II Device Handbook, Volume 1
Figure 2–42. Global & Regional Clock Connections from Corner Clock Pins &
Fast PLL Outputs
Note to
(1)
The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input can be driven by an output from
another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated
global signal cannot drive the PLL.
Figure
2–42:
Note (1)
Altera Corporation
May 2007

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