EP2S60F672C4N Altera, EP2S60F672C4N Datasheet - Page 154

• Manufacturer Part Number: EP2S60F672C4N
• Description: IC STRATIX II FPGA 60K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F672C4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 492
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 492
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1913; EP2S60F672C4N

Operating Conditions
5–18
Stratix II Device Handbook, Volume 1
Notes for
(1)
(2)
50-Ω R
3.3/2.5
50-Ω R
2.5
25-Ω R
1.8
50-Ω R
1.8
50-Ω R
1.8
50−Ω R
1.5
50-Ω R
1.5
50−Ω R
1.2
50-Ω R
1.2
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 2 of 2)
Notes (1)
Symbol
The resistance tolerances for calibrated SOCT and POCT are for the moment of calibration. If the temperature or
voltage changes over time, the tolerance may also change.
On-chip parallel termination with calibration is only supported for input pins.
S
T
S
S
T
T
T
S
S
Table
,
2
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
Internal series termination with
calibration (25-Ω setting)
Internal series termination without
calibration (25-Ω setting)
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
5–30:
Description
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C C I O
C C I O
C C I O
C C I O
C C I O
C C I O
C C I O
C C I O
C C I O
C C I O
C C I O
C C I O
C C I O
C C I O
Conditions
= 3.3/2.5 V
= 3.3/2.5 V
= 1.8 V
= 1.8 V
= 1.8 V
= 1.8 V
= 1.8 V
= 1.8 V
= 1.5 V
= 1.5 V
= 1.5 V
= 1.2 V
= 1.2 V
= 1.2 V
Commercial
Max
±30
±30
±30
±30
±10
±36
±10
±50
±10
±5
±5
±5
±8
±8
Resistance Tolerance
Industrial
Altera Corporation
Max
±10
±30
±30
±10
±30
±10
±30
±15
±10
±36
±15
±10
±50
±15
April 2011
Unit
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%
%
%
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%
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