EP1S80F1020C7 Altera, EP1S80F1020C7 Datasheet - Page 126

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EP1S80F1020C7

Manufacturer Part Number
EP1S80F1020C7
Description
IC STRATIX FPGA 80K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S80F1020C7

Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1440
EP1S80F1020C7

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I/O Structure
Figure 2–65. Stratix IOE in DDR Input I/O Configuration
Notes to
(1)
(2)
(3)
2–112
Stratix Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
I/O Interconnect
Figure
[15..0]
2–65:
ioe_clk[7..0]
(1)
DQS Local
Bus (1), (2)
(1)
sclr
clkin
aclr/prn
Chip-Wide Reset
Enable Delay
Output Clock
Input Register
Input Register
Note (1)
D
ENA
CLRN/PRN
D
CLRN/PRN
ENA
Input Register Delay
Input Pin to
Q
Q
D
ENA
CLRN/PRN
To DQS Local
Latch
Bus (3)
Q
VCCIO
Altera Corporation
VCCIO
Optional
PCI Clamp
Bus-Hold
Circuit
July 2005
Programmable
Pull-Up
Resistor

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