XC3S700AN-4FGG484I Xilinx Inc, XC3S700AN-4FGG484I Datasheet - Page 60
![IC FPGA SPARTAN -3AN700K 484FBGA](/photos/28/18/281821/xc3s700an-4fgg484i_sml.jpg)
XC3S700AN-4FGG484I
Manufacturer Part Number
XC3S700AN-4FGG484I
Description
IC FPGA SPARTAN -3AN700K 484FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S700AN-4FGG484I
Total Ram Bits
368640
Number Of Logic Elements/cells
13248
Number Of Labs/clbs
1472
Number Of I /o
372
Number Of Gates
700000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
No. Of Logic Blocks
1472
No. Of Gates
700000
No. Of Macrocells
13248
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
372
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1528 - KIT STARTER SPARTAN-3 AN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1598
XC3S700AN-4FGG484I
XC3S700AN-4FGG484I
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S700AN-4FGG484I
Manufacturer:
XILINX
Quantity:
325
Company:
Part Number:
XC3S700AN-4FGG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
X-Ref Target - Figure 13
Table 50: Power-On Timing and the Beginning of Configuration
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
T
T
T
T
T
POR
PROG
PL
INIT
ICCK
(2)
The numbers in this table are based on the operating conditions set forth in
and V
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only to the Master Serial, SPI, and BPI modes.
For details on configuration, see
(2)
Symbol
(3)
Notes:
1.
2.
3.
V
CCAUX
(Open-Drain)
CCO
PROG_B
When configuring from the In-System Flash, V
sure V
V
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
(Supply)
V
(Supply)
(Supply)
CCO
V
(Output)
Bank 2
CCAUX
lines.
(Input)
INIT_B
CCINT
CCLK
supplies to the FPGA can be applied in any order if this requirement is met.
CCAUX
The time from the application of V
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
Figure 13: Waveforms for Power-On and the Beginning of Configuration
reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. V
UG332
Spartan-3 Generation Configuration User Guide.
Description
1.0V
2.0V
2.0V
CCINT
CCAUX
T
T
www.xilinx.com
POR
PROG
, V
Spartan-3AN FPGA Family: DC and Switching Characteristics
must be in the recommended operating range; on power-up make
CCAUX
, and V
T
Table
PL
CCO
10. This means power must be applied to all V
All
All
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
All
All
T
Device
ICCK
All Speed Grades
Min
250
0.5
0.5
–
–
–
–
–
–
CCINT
, V
DS557-3_01_052908
CCAUX
Max
0.5
0.5
18
–
1
2
2
–
4
, and
1.2V
3.3V
3.3V
2.5V
or
CCINT
Units
, V
ms
ms
ms
ms
ms
ms
µs
ns
µs
CCO
60
,