AT40K40AL-1BQU Atmel, AT40K40AL-1BQU Datasheet - Page 3
![FPGA 40K GATE 3.3V 1NS 144-LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT40K40AL-1BQU
Manufacturer Part Number
AT40K40AL-1BQU
Description
FPGA 40K GATE 3.3V 1NS 144-LQFP
Manufacturer
Atmel
Series
AT40KALr
Datasheet
1.AT40K05AL-1AQC.pdf
(55 pages)
Specifications of AT40K40AL-1BQU
Number Of Logic Elements/cells
2304
Total Ram Bits
18432
Number Of I /o
114
Number Of Gates
50000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Labs/clbs
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Cache Logic Design
Automatic Component
Generators
2818F–FPGA–07/06
The AT40KAL, AT6000 and FPSLIC families are capable of implementing Cache Logic
(dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building
adaptive logic and systems. As new logic functions are required, they can be loaded into
the logic cache without losing the data already there or disrupting the operation of the
rest of the chip; replacing or complementing the active logic. The AT40KAL can act as a
reconfigurable coprocessor.
The AT40KAL FPGA family is capable of implementing user-defined, automatically gen-
erated, macros in multiple designs; speed and functionality are unaffected by the macro
orientation or density of the target device. This enables the fastest, most predictable and
efficient FPGA design approach and minimizes design risk by reusing already proven
functions. The Automatic Component Generators work seamlessly with industry stan-
dard schematic and synthesis tools to create the fastest, most efficient designs
available.
The patented AT40KAL series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable I/O.
Devices range in size from 5,000 to 50,000 usable gates in the family, and have 256 to
3,048 registers. Pin locations are consistent throughout the AT40KAL series for easy
design migration in the same package footprint. The AT40KAL series FPGAs utilize a
reliable 0.35µ triple-metal, CMOS process and are 100% factory-tested. Atmel’s PC-
and workstation-based integrated development system (IDS) is used to create
AT40KAL series designs. Multiple design entry methods are supported.
The Atmel architecture was developed to provide the highest levels of performance,
functional density and design flexibility in an FPGA. The cells in the Atmel array are
small, efficient and can implement any pair of Boolean functions of (the same) three
inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays
with large numbers of cells, greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient communication over medium and
long distances.
AT40KAL Series FPGA
3