EP2C5Q208I8 Altera, EP2C5Q208I8 Datasheet - Page 20
![IC CYCLONE II FPGA 5K 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EP2C5Q208I8
Manufacturer Part Number
EP2C5Q208I8
Description
IC CYCLONE II FPGA 5K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C5Q208I8
Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
142
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2134
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2C5Q208I8
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2C5Q208I8N
Manufacturer:
Altera
Quantity:
1 948
Company:
Part Number:
EP2C5Q208I8N
Manufacturer:
ALTERA41
Quantity:
228
Part Number:
EP2C5Q208I8N
Manufacturer:
ALTERA
Quantity:
20 000
Logic Array Blocks
Figure 2–6. Direct Link Connection
2–8
Cyclone II Device Handbook, Volume 1
Direct link interconnect from
block, embedded multiplier,
left LAB, M4K memory
PLL, or IOE output
interconnect
Direct link
to left
Interconnect
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, M4K RAM
blocks, and embedded multipliers from the left and right can also drive
an LAB’s local interconnect through the direct link connection. The direct
link connection feature minimizes the use of row and column
interconnects, providing higher performance and flexibility. Each LE can
drive 48 LEs through fast local and direct link interconnects.
shows the direct link connection.
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include:
■
■
■
■
■
Local
Two clocks
Two clock enables
Two asynchronous clears
One synchronous clear
One synchronous load
LAB
Direct link
interconnect
to right
Direct link interconnect from
right LAB, M4K memory
block, embedded multiplier,
PLL, or IOE output
Altera Corporation
February 2007
Figure 2–6