EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 69
![IC CYCLONE III FPGA 5K 144 EQFP](/photos/6/73/67369/ep3c5e144i7n_sml.jpg)
EP3C5E144I7N
Manufacturer Part Number
EP3C5E144I7N
Description
IC CYCLONE III FPGA 5K 144 EQFP
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C5E144I7N.pdf
(274 pages)
Specifications of EP3C5E144I7N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
94
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-EQFP
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2557
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5E144I7N
Manufacturer:
Altera
Quantity:
135
Company:
Part Number:
EP3C5E144I7N
Manufacturer:
ALTERA32
Quantity:
345
Part Number:
EP3C5E144I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 2: Cyclone III LS Device Data Sheet
I/O Timing
Table 2–38. Cyclone III LS Devices IOE Programmable Delay on Row Pins
I/O Timing
© December 2009
Input delay from the pin to the
internal cells
Input delay from the pin to the
input register
Delay from the output register to
the output pin
Input delay from the
dual-purpose clock pin to the
fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers refer to the 0 setting available in the Quartus II software.
Table
Parameter
f
f
2–38:
Altera Corporation
DirectDrive technology and MultiTrack interconnect ensure predictable performance,
accurate simulation, and accurate timing analysis across all Cyclone III LS device
densities and speed grades.
Use the following methods to determine I/O timing:
■
■
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used before designing the FPGA to get a timing
budget estimation as part of the link timing analysis. The Quartus II Timing Analyzer
provides a more accurate and precise I/O timing data based on the specifics of the
design after place-and-route is complete.
For more information about the Excel-based I/O timing spreadsheet, refer to the
Cyclone III Devices
All specifications are representative of worst-case supply voltage and junction
temperature conditions. Altera characterizes timing delays at the worst-case process,
minimum voltage, and maximum temperature for input register setup time (t
hold time (t
For more information about timing delay from the FPGA output to the receiving
device for system-timing analysis, refer to
for Altera Devices.
The Excel-based I/O timing
The Quartus II Timing Analyzer
Pad to I/O
dataout to core
Pad to I/O input
register
I/O output
register to pad
Pad to global
clock network
H
Paths Affected
).
Literature page on the Altera website.
Number
setting
12
of
7
8
2
Offset
Min
0
0
0
0
AN 366: Understanding I/O Output Timing
(Note
1.209 1.314 2.352 2.514 2.432
1.207 1.312 2.402 2.558 2.447
0.549 0.595 1.135 1.226 1.151
0.52
Fast Corner
I7
1),
(2)
0.54
C7
Max Offset
Cyclone III Device Handbook, Volume 2
1.052
C7
Slow Corner
1.16
C8
1.061
I7
SU
) and
Unit
ns
ns
ns
ns
2–25