EP4CE10E22C8LN Altera, EP4CE10E22C8LN Datasheet - Page 308

• Manufacturer Part Number: EP4CE10E22C8LN
• Description: IC CYCLONE IV FPGA 10K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE10E22C8LN

• Number Of Logic Elements/cells: 10320
• Number Of Labs/clbs: 645
• Total Ram Bits: 414000
• Number Of I /o: 91
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–28
Table 1–8. Supported Conditions in Non-Bonded and Bonded Channel Configurations
Cyclone IV Device Handbook, Volume 2
Configuration
Non-bonded
(×1)
Bonded (×2
and ×4)
Channel
1
1
■
■
■
■
■
■
Low-speed clock in each channel is sourced independently
Phase compensation FIFO in each channel has its own pointers and control logic
Low-speed clock in each bonded channel is sourced from a common bonded clock
path for lower channel-to-channel skew
Phase compensation FIFOs in bonded channels share common pointers and control
logic for equal latency through the FIFOs in all bonded channels
×2 bonded configuration is supported with channel 0 and channel 1 in a transceiver
block
×4 bonded configuration is supported with all four channels in a transceiver block
In any configuration, a receiver channel cannot source CDR clocks from other PLLs
beyond the two multipurpose PLLs directly adjacent to transceiver block where the
channel resides.
The Cyclone IV GX transceivers support non-bonded (×1) and bonded (×2 and ×4)
channel configurations. The two configurations differ in regards to clocking and
phase compensation FIFO control. Bonded configuration provides a relatively lower
channel-to-channel skew between the bonded channels than in non-bonded
configuration.
channel configurations.
Non-Bonded Channel Configuration
In non-bonded channel configuration, the high- and low-speed clocks for each
channel are sourced independently. The phase compensation FIFOs in each channel
has its own pointers and control logic. When implementing multi-channel serial
interface in non-bonded channel configuration, the clock skew and unequal latency
results in larger channel-to-channel skew.
Altera recommends using bonded channel configuration (×2 or ×4) when
implementing multi-channel serial interface for a lower channel-to-channel skew.
In a transceiver block, the high- and low-speed clocks for each channel are distributed
primarily from one of the two multipurpose PLLs directly adjacent to the block.
Transceiver channels for devices in F484 and larger packages support additional
clocking flexibility. In these packages, some channels support high-speed and low-
speed clock distribution from PLLs beyond the two multipurpose PLLs directly
adjacent to the block.
Table 1–8
lists the supported conditions in non-bonded and bonded
Description
Chapter 1: Cyclone IV Transceivers Architecture
© December 2010 Altera Corporation
Transceiver Clocking Architecture
■
■
■
■
■
Supported Channel
Operation Mode
Transmitter Only
Receiver Only
Transmitter and
Receiver
Transmitter Only
Transmitter and
Receiver