EPF6016TI144-3N Altera, EPF6016TI144-3N Datasheet - Page 24
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EPF6016TI144-3N
Manufacturer Part Number
EPF6016TI144-3N
Description
IC FLEX 6000 FPGA 16K 144-TQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet
1.EPF6010ATC100-3N.pdf
(52 pages)
Specifications of EPF6016TI144-3N
Number Of Logic Elements/cells
1320
Number Of Labs/clbs
132
Number Of I /o
117
Number Of Gates
16000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Total Ram Bits
-
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FLEX 6000 Programmable Logic Device Family Data Sheet
24
Each IOE drives a row or column interconnect when used as an input or
bidirectional pin. A row IOE can drive up to six row lines; a column IOE
can drive up to two column lines. The input path from the I/O pad to the
FastTrack Interconnect has a programmable delay element that can be
used to guarantee a zero hold time. Depending on the placement of the
IOE relative to what it is driving, the designer may choose to turn on the
programmable delay to ensure a zero hold time.
IOE connects to a row interconnect, and
connects to a column interconnect.
Figure 13. IOE Connection to Row Interconnect
Any LE can drive
a pin through the
row and local
interconnect.
Row Interconnect
LAB
FastFLEX I/O: An LE can drive a pin through the
local interconnect for faster clock-to-output times.
IOE
IOE
Figure 14
Figure 13
Up to 10 IOEs are on either
side of a row. Each IOE can
drive up to six row
channels, and each IOE data
and OE signal is driven by
the local interconnect.
shows how an IOE
Altera Corporation
shows how an