EP3C16F484C7 Altera, EP3C16F484C7 Datasheet - Page 2

IC CYCLONE III FPGA 16K 484FBGA

EP3C16F484C7

Manufacturer Part Number
EP3C16F484C7
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C16F484C7

Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2470

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Page 2
Table 1. Cyclone III FPGA Device Family Features
I/O Pin Count, Package Offering and Vertical Migration
Logic Elements
Memory (Kbits)
Multipliers
PLLs
Global Clock Networks
Feature
f
1
The Cyclone III device family offers up to a maximum of 535 user I/O pins.
Depending on your application and board layout, you can choose to use the Quad
Flat Pack (QFP), FineLine Ball Grid Array (FBGA) with a 1.0 mm ball pitch or the
Ultra FBGA package (UBGA) with an 0.8 mm ball pitch. The 0.8 mm ball pitch is the
smallest in the Cyclone III device family and it also saves board space.
Cyclone III devices support vertical migration within the same package. For a given
package, the devices across different densities have the same locations for the power
pins, configuration pins and dedicated pins. This allows future upgrade or changes to
your Cyclone III design without having to change the board layout as you can replace
the Cyclone III device in your board with another Cyclone III device of a different
density. For best results, you can specify the migration device before compiling your
initial design with the Quartus II software to ensure that only pins that are available
in the same locations on both devices are used in the design for seamless migration to
a larger or smaller device.
The number of differential channels may vary across device density.
For more information about the number of differential channels available for different
densities and packages of the Cyclone III device family, refer to the
Differential Interfaces in Cyclone III Devices
Handbook.
Table 2
family across device density. The vertical arrows indicate the vertical migration for the
devices in a given package.
EP3C5
5,136
414
shows the number of user I/O pins and package offerings for the Cyclone III
23
10
2
EP3C10
10,320
414
23
10
2
EP3C16
15,408
504
56
20
4
EP3C25
24,624
594
66
20
4
chapter in volume 1 of the Cyclone III Device
EP3C40
39,600
1,134
126
20
4
EP3C55
55,856
2,340
© November 2008 Altera Corporation
156
20
4
EP3C80
81,264
2,745
High-Speed
244
20
4
Device Selection
EP3C120
119,088
3,888
288
20
4

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