EP1C12F324I7 Altera, EP1C12F324I7 Datasheet - Page 55
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EP1C12F324I7
Manufacturer Part Number
EP1C12F324I7
Description
IC CYCLONE FPGA 12K LE 324-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C12F324I7
Number Of Logic Elements/cells
12060
Number Of Labs/clbs
1206
Total Ram Bits
239616
Number Of I /o
249
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone®
Number Of Logic Blocks/elements
12060
# I/os (max)
249
Frequency (max)
320.1MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
12060
Ram Bits
239616
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1037
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C12F324I7
Manufacturer:
ALTERA
Quantity:
12 388
Part Number:
EP1C12F324I7
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1C12F324I7N
Manufacturer:
ALTERA
Quantity:
339
Company:
Part Number:
EP1C12F324I7N
Manufacturer:
ALTERA32
Quantity:
96
Part Number:
EP1C12F324I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–34. DDR SDRAM and FCRAM Interfacing
Altera Corporation
May 2008
PLL
OE
Phase Shifted -90˚
Register
OE LE
Register
OE LE
GND
V
CC
Output LE
Output LE
Register
Register
Programmable Drive Strength
The output buffer for each Cyclone device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standards have several levels of drive strength that the designer
can control. SSTL-3 class I and II, and SSTL-2 class I and II support a
minimum setting, the lowest drive strength that guarantees the I
Programmable
Delay Chain
clk
DQS
Δ t
OE
Register
OE LE
Global Clock
Register
OE LE
DataA
DataB
Output LE
Output LE
Registers
Registers
-90˚ clk
DQ
Adjacent LAB LEs
Register
Register
LE
LE
Registers
Registers
Input LE
Input LE
I/O Structure
Preliminary
Adjacent
LAB LEs
Resynchronizing
Global Clock
OH
/I
2–49
OL