EP2C20F484C6N Altera, EP2C20F484C6N Datasheet - Page 158
![IC CYCLONE II FPGA 20K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2C20F484C6N
Manufacturer Part Number
EP2C20F484C6N
Description
IC CYCLONE II FPGA 20K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C20F484C6N
Number Of Logic Elements/cells
18752
Number Of Labs/clbs
1172
Total Ram Bits
239616
Number Of I /o
315
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
18752
# I/os (max)
315
Frequency (max)
500MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
18752
Ram Bits
239616
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
For Use With
P0528 - BOARD DEV DE1 ALTERA544-1736 - CYCLONE II STARTER KIT EP2C20N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1670
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Duty Cycle Distortion
Figure 5–9. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
5–68
Cyclone II Device Handbook, Volume 1
clk
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions
present on the input clock signal, or caused by the clock input buffer, or
different input I/O standard, does not transfer to the output signal.
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions
clock and the input clock buffer affect the output DCD.
IOE
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
(Figure
DFF
D
5–10). Therefore, any distortion on the input
Q
(Figure
5–9). Therefore, any DCD
Altera Corporation
output
February 2008
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