EPF10K30AQC208-3N Altera, EPF10K30AQC208-3N Datasheet - Page 7
![IC FLEX 10KA FPGA 30K 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EPF10K30AQC208-3N
Manufacturer Part Number
EPF10K30AQC208-3N
Description
IC FLEX 10KA FPGA 30K 208-PQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K30AQC208-3N
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
12288
Number Of I /o
147
Number Of Gates
69000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1939
EPF10K30AQC208-3N
EPF10K30AQC208-3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Altera Corporation
Functional
Description
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For more information, see the following documents:
FLEX 10K devices are supported by Altera development systems; single,
integrated packages that offer schematic, text (including AHDL), and
waveform design entry, compilation and logic synthesis, full simulation
and worst-case timing analysis, and device configuration. The Altera
software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and
other interfaces for additional design entry and simulation support from
other industry-standard PC- and UNIX workstation-based EDA tools.
The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use device-
specific features such as carry chains which are used for fast counter and
arithmetic functions. For instance, the Synopsys Design Compiler library
supplied with the Altera development systems include DesignWare
functions that are optimized for the FLEX 10K architecture.
The Altera development systems run on Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations.
See the MAX+PLUS II Programmable Logic Development System & Software
Data Sheet for more information.
Each FLEX 10K device contains an embedded array to implement
memory and specialized logic functions, and a logic array to implement
general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 2,048 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions, such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
Configuration Devices for APEX & FLEX Devices Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000
Devices)
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
7