EP1C20F324C6 Altera, EP1C20F324C6 Datasheet - Page 45
![IC CYCLONE FPGA 20K LE 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP1C20F324C6
Manufacturer Part Number
EP1C20F324C6
Description
IC CYCLONE FPGA 20K LE 324-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C20F324C6
Number Of Logic Elements/cells
20060
Number Of Labs/clbs
2006
Total Ram Bits
294912
Number Of I /o
233
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1038
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C20F324C6
Manufacturer:
ALTERA
Quantity:
745
Part Number:
EP1C20F324C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1C20F324C6N
Manufacturer:
HONDA
Quantity:
2 000
Company:
Part Number:
EP1C20F324C6N
Manufacturer:
ALTERA
Quantity:
853
I/O Structure
Altera Corporation
May 2008
IOEs support many features, including:
■
■
■
■
■
■
■
■
■
■
■
■
Cyclone device IOEs contain a bidirectional I/O buffer and three registers
for complete embedded bidirectional single data rate transfer.
Figure 2–27
register, one output register, and one output enable register. You can use
the input registers for fast setup times and output registers for fast
clock-to-output times. Additionally, you can use the output enable (OE)
register for fast clock-to-output enable timing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins. IOEs can be used as input, output, or
bidirectional pins.
Differential and single-ended I/O standards
3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Output drive strength control
Weak pull-up resistors during configuration
Slew-rate control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors in user mode
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
shows the Cyclone IOE structure. The IOE contains one input
I/O Structure
Preliminary
2–39