EP1C20F400I7 Altera, EP1C20F400I7 Datasheet - Page 96
EP1C20F400I7
Manufacturer Part Number
EP1C20F400I7
Description
IC CYCLONE FPGA 20K LE 400-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C20F400I7
Number Of Logic Elements/cells
20060
Number Of Labs/clbs
2006
Total Ram Bits
294912
Number Of I /o
301
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
400-FBGA
Family Name
Cyclone®
Number Of Logic Blocks/elements
20060
# I/os (max)
301
Frequency (max)
320.1MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
20060
Ram Bits
294912
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
400
Package Type
FBGA
No. Of Logic Blocks
2006
No. Of Macrocells
20060
Family Type
Cyclone
No. Of Speed Grades
7
No. Of I/o's
301
Clock Management
PLL
I/o Supply Voltage
4.1V
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1049
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C20F400I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1C20F400I7
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1C20F400I7N
Manufacturer:
ALTERA31
Quantity:
1 201
Part Number:
EP1C20F400I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Cyclone Device Handbook, Volume 1
4–26
Preliminary
Note to
(1)
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Decrease input delay to
internal cells
Decrease input delay to
input register
Increase delay to output
pin
Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2)
Table 4–46. Cyclone IOE Programmable Delays on Column Pins
EP1C3 devices do not support the PCI I/O standard.
I/O Standard
Parameter
Tables 4–40
through 4–45:
Off
Small
Medium
Large
On
Off
On
Off
On
Setting
Tables 4–46
programmable delays. These delays are controlled with the Quartus II
software options listed in the Parameter column.
-6 Speed Grade
Min
—
—
—
—
—
-6 Speed Grade
through
Min
1,390
1,965
1,692
Max
—
—
—
—
—
—
—
—
—
989
802
2,122
2,639
3,057
3,057
4–47
Max
155
155
552
0
0
-7 Speed Grade
Min
—
—
—
—
—
show the adder delays for the IOE
-7 Speed Grade
Min
—
—
—
—
—
—
—
—
—
1,598
1,137
2,259
1,945
Max
922
2,543
3,034
3,515
3,515
Max
178
178
634
0
0
-8 Speed Grade
Min
—
—
—
—
—
-8 Speed Grade
Min
—
—
—
—
—
—
—
—
—
Altera Corporation
1,807
1,285
2,554
2,199
1,042
Max
2,875
3,430
3,974
3,974
Max
201
201
717
0
0
May 2008
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps