EP3C40F780C8N Altera, EP3C40F780C8N Datasheet - Page 42
![IC CYCLONE III FPGA 40K 780FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP3C40F780C8N
Manufacturer Part Number
EP3C40F780C8N
Description
IC CYCLONE III FPGA 40K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F780C8N.pdf
(274 pages)
Specifications of EP3C40F780C8N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
535
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
535
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2504
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F780C8N
Manufacturer:
ALTERA
Quantity:
364
1–32
Document Revision History
Table 1–40. Document Revision History
Cyclone III Device Handbook, Volume 2
January 2010
December 2009
July 2009
June 2009
October 2008
July 2008
Date
Table 1–40
Version
3.3
3.2
3.1
3.0
2.2
2.1
lists the revision history for this chapter.
(Part 1 of 3)
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Minor changes to the text.
Minor edit to the hyperlinks.
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Removed Table 1-32 and Table 1-33.
Added
Changed chapter title from DC and Switching Characteristics to “Cyclone III
Device Data Sheet” on page 1–1.
Updated (Note 1) to Table 1–23 on page 1–17.
Updated “External Memory Interface Specifications” on page 1–23.
Replaced Table 1–32 on page 1–23.
Replaced Table 1–33 on page 1–23.
Added Table 1–36 on page 1–26.
Updated “I/O Timing” on page 1–28.
Removed “Typical Design Performance” section.
Removed “I/O Timing” subsections.
Updated chapter to new template.
Updated Table 1–1, Table 1–3, and Table 1–18.
Added (Note 7) to Table 1–3.
Added the “OCT Calibration Timing Specification” section.
Updated “Glossary” section.
Updated Table 1–38.
Added BLVDS information (I/O standard) into Table 1–39, Table 1–40,
Table 1–41, Table 1–42.
Updated Table 1–43, Table 1–46, Table 1–47, Table 1–48, Table 1–49,
Table 1–50, Table 1–51, Table 1–52, Table 1–53, Table 1–54, Table 1–55,
Table 1–56, Table 1–57, Table 1–58, Table 1–59, Table 1–60, Table 1–61,
Table 1–62, Table 1–63, Table 1–68, Table 1–69, Table 1–74, Table 1–75,
Table 1–80, Table 1–81, Table 1–86, Table 1–87, Table 1–92, Table 1–93,
Table 1–94, Table 1–95, Table 1–96, Table 1–97, Table 1–98, and Table 1–99.
Literature: External Memory Interfaces
Changes Made
Chapter 1: Cyclone III Device Data Sheet
© January 2010 Altera Corporation
reference.
Document Revision History