EP3C40F324I7N Altera, EP3C40F324I7N Datasheet - Page 70
EP3C40F324I7N
Manufacturer Part Number
EP3C40F324I7N
Description
IC CYCLONE III FPGA 40K 324 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F324I7N.pdf
(274 pages)
Specifications of EP3C40F324I7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
195
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
195
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2547
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA31
Quantity:
129
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C40F324I7N PDF datasheet #6
- Current page: 70 of 274
- Download datasheet (6Mb)
5–6
GCLK Network Clock Source Generation
Figure 5–2. PLL, CLK[], DPCLK[], and Clock Control Block Locations in the Cyclone III Device Family
Notes to
(1) There are five clock control blocks on each side.
(2) Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. You can use the other CDPCLK pins as
(3) Remote clocks cannot be used to feed the PLLs.
(4) Dedicated clock paths can feed into this PLL. However, these paths are not fully compensated.
Cyclone III Device Handbook, Volume 1
CDPCLK0
CDPCLK1
CLK[3..0]
DPCLK1
DPCLK0
general-purpose I/O pins.
Figure
5–2:
4
Figure 5–2
block location for different device densities.
PLL
(4)
4
PLL
4
1
3
5
CDPCLK2
CDPCLK7
(2)
(2)
shows Cyclone III device family PLLs, clock inputs, and clock control
(4)
Clock Control
2
2
4
4
Block (1)
GCLK[19..0]
5
DPCLK[11.10]
DPCLK[3..2]
20
2
2
CLK[15..12]
CLK[11..8]
20
20
4
4
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
DPCLK[9..8]
DPCLK[5..4]
20
GCLK[19..0]
2
2
Clock Control
Block (1)
Remote clock from
two clock pins at
adjacent edge of
device
(4)
2
4
(3)
2
4
5
CDPCLK6
CDPCLK3
(2)
(2)
© December 2009 Altera Corporation
5
PLL
(4)
PLL
4
2
4
4
(Note 1)
4
Clock Networks
CDPCLK5
DPCLK7
CLK[7..4]
DPCLK6
CDPCLK4
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