EP3C40F324I7N Altera, EP3C40F324I7N Datasheet - Page 29
![IC CYCLONE III FPGA 40K 324 FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C40F324I7N
Manufacturer Part Number
EP3C40F324I7N
Description
IC CYCLONE III FPGA 40K 324 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F324I7N.pdf
(274 pages)
Specifications of EP3C40F324I7N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
195
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
195
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2547
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA31
Quantity:
129
Part Number:
EP3C40F324I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Design and Compilation
© November 2008 Altera Corporation
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For the specific HDL coding examples and recommendations, refer to the
Recommended HDL Coding Styles
to your synthesis tool's documentation for any additional tool-specific guidelines. In
the Quartus II software, you can use the HDL examples in the Language Templates
available from the right-click menu in the text editor.
The Quartus II software is able to generate the symbol or HDL files for the
megafunctions you create and allows you to integrate the megafunction into your
design, regardless of the design entry method. You can also generate the symbol file
for certain blocks in your design written in HDL. With that, your design can have a
mixture of HDL and schematic entry. You can infer certain device resources, for
example the memory, through HDL as well.
Selecting a Synthesis Tool
The Quartus II software can synthesize design entries in Verilog HDL, VHDL, Altera
hardware description language (AHDL) and schematics. You can also use third-party
EDA synthesis tools to synthesize your Verilog or VHDL design, and then use the
Quartus II software to perform the placement and routing based on the generated
netlist. Specify the third-party synthesis tool in the New Project Wizard or the EDA
Tools Settings page of the Settings dialog box to use the correct Library Mapping File
for your synthesis netlist.
Your synthesis tool might offer the capability to create a Quartus II project and pass
constraints such as the EDA tool setting, device selection, and timing requirements
that you specified in your synthesis project. You can use this capability to save time
when setting up your Quartus II project for placement and routing.
Altera recommends using the most recent version of the third-party synthesis tools,
because tool vendors are continuously adding new features, fixing tool issues, and
enhancing performance for Altera devices. The EDA tools that can generate the netlist
for the Quartus II Fitter include Synplicity Synplify and SynplifyPro software,
Synopsys Design Compiler, and Mentor Graphics
and LeonardoSpectrum
netlist file in either EDIF Input File (.edf) or Verilog Quartus Mapped (.vqm) format.
For more information on the supported synthesis tools, refer to the appropriate
chapter in
Notes list the version of each synthesis tool that is officially supported by that version
of the Quartus II software.
SOPC Builder
The System-on-a-Programmable-Chip (SOPC) Builder system generation tool is
useful for creating systems based on processors, peripherals, and memories. SOPC
Builder allows you to build your SOPC in less time as you do not need to create the
designs for all the components in your system. The SOPC system can be a standalone
system, or you can integrate the SOPC system into your custom logic design. The
SOPC Builder comes together with the Quartus II software.
For more information about the SOPC Builder and how to build your SOPC system
with the SOPC Builder, refer to the Altera website at
www.altera.com/products/software/products/sopc/sop-index.html
SOPC Builder
Synthesis
of the Quartus II Handbook.
in volume 1 of the Quartus II Handbook. The Quartus II Release
™
software. The EDA tools normally generate the design
chapter in volume 1 of the Quartus II Handbook. Refer
®
Precision RTL Synthesis software,
or
Volume 4:
Page 29