EPF10K30RC208-4 Altera, EPF10K30RC208-4 Datasheet - Page 11
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EPF10K30RC208-4
Manufacturer Part Number
EPF10K30RC208-4
Description
IC FLEX 10K FPGA 30K 208-RQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K30RC208-4
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
12288
Number Of I /o
147
Number Of Gates
69000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-RQFP
Family Name
FLEX 10K
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# Registers
738
# I/os (max)
147
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
5V
Logic Cells
1728
Ram Bits
12288
Device System Gates
69000
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
RQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2229
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K30RC208-4
Manufacturer:
ALTERA
Quantity:
5 530
Part Number:
EPF10K30RC208-4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPF10K30RC208-4N
Manufacturer:
ALTERA11
Quantity:
419
Part Number:
EPF10K30RC208-4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256
256 16 RAM block; two 512
a 512 8 RAM block. See
Figure 3. Examples of Combining EABs
If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timing. Altera’s software automatically combines
EABs to meet a designer’s RAM specifications.
EABs provide flexible options for driving and controlling clock signals.
Different clocks can be used for the EAB inputs and outputs. Registers can
be independently inserted on the data input, EAB output, or the address
and WE inputs. The global signals and the EAB local interconnect can drive
the WE signal. The global signals, dedicated clock pins, and EAB local
interconnect can drive the EAB clock signals. Because the LEs drive the
EAB local interconnect, the LEs can control the WE signal or the EAB clock
signals.
Each EAB is fed by a row interconnect and can drive out to row and
column interconnects. Each EAB output can drive up to two row channels
and up to two column channels; the unused row channel can be driven by
other LEs. This feature increases the routing resources available for EAB
outputs. See
256
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
256
8
8
Figure
256
8 RAM blocks can be combined to form a
4.
16
Figure
4 blocks of RAM can be combined to form
3.
512
512
512
8
11