EPF10K50EQC240-3N Altera, EPF10K50EQC240-3N Datasheet - Page 52
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EPF10K50EQC240-3N
Manufacturer Part Number
EPF10K50EQC240-3N
Description
IC FLEX 10KE FPGA 50K 240-PQFP
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K50EQC240-3N
Number Of Logic Elements/cells
2880
Number Of Labs/clbs
360
Total Ram Bits
40960
Number Of I /o
189
Number Of Gates
199000
Voltage - Supply
2.3 V ~ 2.7 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KE
Number Of Usable Gates
50000
Number Of Logic Blocks/elements
2880
# Registers
189
# I/os (max)
189
Frequency (max)
166.67MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
2880
Ram Bits
40960
Device System Gates
199000
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
2.7V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K50EQC240-3N
Manufacturer:
ALTERA
Quantity:
20 000
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 23. Output Drive Characteristics of FLEX 10KE Devices
Note:
(1)
Timing Model
52
These are transient (AC) currents.
Typical I
Output
Current (mA)
O
30
20
10
90
80
70
60
50
40
V
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
O
1
V
V
Room Temperature
Output Voltage (V)
CCINT
CCIO
LE register clock-to-output delay (t
Interconnect delay (t
LE look-up table delay (t
LE register setup time (t
= 2.5
= 2.5
2
V
I
OH
V
I
OL
3
Typical I
Output
Current (mA)
SAMEROW
O
SU
LUT
)
)
30
20
10
90
80
70
60
50
40
Note (1)
)
CO
V
)
O
1
Output Voltage (V)
2
V
V
Room Temperature
I
Altera Corporation
OL
CCINT
CCIO
3
I
OH
= 3.3
= 2.5
V
V