EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 4

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Page 4
Pin Connection Guidelines Update for Transceiver Applications that
Run at ≥ 2.97 Gbps Data Rate
Table 3. Reference Clock Pins and the Associated I/O Pins to be Grounded for ≥ 2.97 Gbps Transceiver
Applications (Part 1 of 3)
Errata Sheet for Cyclone IV Devices
Package
F23
Workaround
REFCLK[1..0]
Reference
REFCLK2
Clock
A workaround is being implemented in the ALTREMOTE_UPDATE megafunction
and will be available in the future Quartus
questions, contact Altera Technical Support at www.altera.com/support.
You may not meet the protocol jitter specification or may have a higher bit error rate
(BER) if you do not use the following guidelines.
If your transceiver applications run at ≥ 2.97 Gbps data rate, you must ground specific
pins (refer to
device to the PCB ground plane on your board. You also must assign the specific pins
to ground in the Quartus II software. To minimize the impact listed in
recommends using REFCLK[1..0] and REFCLK[5..4] reference clocks before using
REFCLK2 and REFCLK3 reference clocks.
There is no action required and no performance degradation for input reference clocks
that are used to drive transceiver channels at < 2.97 Gbps data rates.
Table 3
transceiver applications that run at ≥ 2.97 Gbps data rate.
lists the reference clock pins and the associated I/O pins to be grounded for
3B
3A
Bank
Pin Connection Guidelines Update for Transceiver Applications that Run at ≥ 2.97 Gbps Data Rate
Table
(1)
(2)
3) next to the reference clock directly through the via under the
Clock Pins
Reference
M11
N11
M7
M8
N7
N8
AA4 (CRC_ERROR)
W8 (INIT_DONE)
I/O Pins to Ground
®
AB3 (nCEO)
II software release. If you have any
AB10
AB11
W12
W13
R13
T13
T7
T8
V6
(5)
(5)
(5)
MPLL_5 and/or GPLL_1
ZDB mode is not
supported.
If you use a DDR system,
the following DQ groups
will not be supported (8):
■
■
■
■
March 2011 Altera Corporation
DQ4B in × 8 groups
DQ5B in × 8/× 9 groups
DQ3B and DQ5B in
× 16/× 18 groups
DQ5B in × 32/× 36
groups
Table
Impact
(7)
3, Altera