EP3C55F484C7N Altera, EP3C55F484C7N Datasheet - Page 97
EP3C55F484C7N
Manufacturer Part Number
EP3C55F484C7N
Description
IC CYCLONE III FPGA 55K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C55F484C7N.pdf
(274 pages)
Specifications of EP3C55F484C7N
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2396160
Number Of I /o
327
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
55856
# I/os (max)
327
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
55856
Ram Bits
2396160
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
3491
Family Type
Cyclone III
No. Of I/o's
327
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2509
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C55F484C7N PDF datasheet #7
- Current page: 97 of 274
- Download datasheet (6Mb)
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Chapter Revision History
Chapter Revision History
Table 5–11. Chapter Revision History (Part 1 of 2)
© December 2009
December 2009
July 2009
June 2009
October 2008
May 2008
September 2007
Date
Altera Corporation
Table 5–11
Version
3.2
3.1
3.0
2.1
2.0
1.2
lists the revision history for this chapter.
Minor changes to the text.
Made minor correction to the part number.
Updated to include Cyclone III LS information
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Updated chapter part number.
Updated “Clock Networks” on page 5–1.
Updated Table 5–1 on page 5–2, Table 5–3 on page 5–9.
Updated “PLLs in the Cyclone III Device Family” on page 5–9.
Updated “PLL Reconfiguration Hardware Implementation” on page 5–25.
Updated “Spread-Spectrum Clocking” on page 5–32.
Updated the “Dynamic Phase Shifting” and “Introduction” sections.
Updated Figure 5–2, Figure 5–8, and Figure 5–24.
Updated chapter to new template.
Updated Figure 5–2 and added (Note 3).
Updated “clkena Signals” section.
Updated Figure 5–8 and added (Note 3).
Updated “PLL Control Signals” section.
Updated “PLL Cascading” section.
Updated “Cyclone III PLL Hardware Overview” section.
Updated Table 5–6, Table 5–3, Table 5–7.
Updated Figure 5–14.
Updated “PLL Cascading” section.
Updated “Clock Multiplication and Division” section.
Updated Step 6–32 in “PLL Reconfiguration Hardware Implementation” section.
Updated “Spread-Spectrum Clocking” section.
Updated Figure 5–29.
Updated “VCCD and GND” section.
Added “Power Consumption” section.
Updated “Board Layout” section and removed Figure 5-30.
Changes Made
Cyclone III Device Handbook, Volume 1
5–33
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