EPF10K30RI240-4 Altera, EPF10K30RI240-4 Datasheet - Page 55
![IC FLEX 10K FPGA 30K 240-RQFP](/photos/6/70/67070/544-240-rqfp_sml.jpg)
EPF10K30RI240-4
Manufacturer Part Number
EPF10K30RI240-4
Description
IC FLEX 10K FPGA 30K 240-RQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K30RI240-4
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
12288
Number Of I /o
189
Number Of Gates
69000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-RQFP
Family Name
FLEX 10K
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# Registers
738
# I/os (max)
189
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
5V
Logic Cells
1728
Ram Bits
12288
Device System Gates
69000
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
RQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2234
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K30RI240-4
Manufacturer:
ALTERA
Quantity:
5 510
Company:
Part Number:
EPF10K30RI240-4N
Manufacturer:
ALTEAR
Quantity:
500
Altera Corporation
Figure 23. Output Drive Characteristics for EPF10K250A Device
Timing Model
Typical I
Output
Current (mA)
O
30
20
10
50
40
1
V
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
O
V
V
Room Temperature
2
Output Voltage (V)
CCI NT
CCI O
LE register clock-to-output delay (t
Interconnect delay (t
LE look-up table delay (t
LE register setup time (t
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
= 3.3 V
3
I
= 3.3 V
OH
I
OL
4
SAMEROW
Typical I
Output
Current (mA)
SU
LUT
)
)
O
)
30
20
10
50
40
CO
)
1
V
O
2
Output Voltage (V)
V
V
Room Temperature
CCI NT
CCI O
I
OH
= 2.5 V
3
= 3.3 V
I
OL
4
55