EP20K200EFC484-3 Altera, EP20K200EFC484-3 Datasheet - Page 21

IC APEX 20KE FPGA 200K 484-FBGA

EP20K200EFC484-3

Manufacturer Part Number
EP20K200EFC484-3
Description
IC APEX 20KE FPGA 200K 484-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet

Specifications of EP20K200EFC484-3

Number Of Logic Elements/cells
8320
Number Of Labs/clbs
832
Total Ram Bits
81920
Number Of I /o
376
Number Of Gates
404000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
APEX 20K
Number Of Usable Gates
200000
Number Of Logic Blocks/elements
8320
# Registers
52
# I/os (max)
376
Frequency (max)
189MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
8320
Ram Bits
106496
Device System Gates
526000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1099

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Figure 9. APEX 20K Interconnect Structure
Column
Interconnect
I/O
I/O
I/O
Row
Interconnect
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
A row line can be driven directly by LEs, IOEs, or ESBs in that row.
Further, a column line can drive a row line, allowing an LE, IOE, or ESB to
drive elements in a different row via the column and row interconnect.
The row interconnect drives the MegaLAB interconnect to drive LEs,
IOEs, or ESBs in a particular MegaLAB structure.
A column line can be directly driven by LEs, IOEs, or ESBs in that column.
A column line on a device’s left or right edge can also be driven by row
IOEs. The column line is used to route signals from one row to another. A
column line can drive a row line; it can also drive the MegaLAB
interconnect directly, allowing faster connections between rows.
Figure 10
interconnect to drive LEs within MegaLAB structures.
MegaLAB
MegaLAB
MegaLAB
shows how the FastTrack Interconnect uses the local
I/O
I/O
APEX 20K Programmable Logic Device Family Data Sheet
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
I/O
I/O
I/O
Column
Interconnect
21

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