EPF10K50EQI240-2 Altera, EPF10K50EQI240-2 Datasheet - Page 9
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EPF10K50EQI240-2
Manufacturer Part Number
EPF10K50EQI240-2
Description
IC FLEX 10KE FPGA 50K 240-PQFP
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K50EQI240-2
Number Of Logic Elements/cells
2880
Number Of Labs/clbs
360
Total Ram Bits
40960
Number Of I /o
189
Number Of Gates
199000
Voltage - Supply
2.3 V ~ 2.7 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KE
Number Of Usable Gates
50000
Number Of Logic Blocks/elements
2880
# Registers
189
# I/os (max)
189
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
2880
Ram Bits
40960
Device System Gates
199000
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
2.7V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1945
EPF10K50EQI240-2
EPF10K50EQI240-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K50EQI240-2
Manufacturer:
NEC
Quantity:
10
Company:
Part Number:
EPF10K50EQI240-2N
Manufacturer:
ALTERA22
Quantity:
209
Altera Corporation
Figure 1. FLEX 10KE Device Block Diagram
Column
Interconnect
I/O Element
(IOE)
Row
Interconnect
Logic
Array
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Figure 1
group of LEs is combined into an LAB; groups of LABs are arranged into
rows and columns. Each row also contains a single EAB. The LABs and
EABs are interconnected by the FastTrack Interconnect routing structure.
IOEs are located at the end of each row and column of the FastTrack
Interconnect routing structure.
FLEX 10KE devices provide six dedicated inputs that drive the flipflops’
control inputs and ensure the efficient distribution of high-speed, low-
skew (less than 1.5 ns) control signals. These signals use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global signals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generated asynchronous clear signal that clears many registers in the
device.
IOE
IOE
IOE
IOE
shows a block diagram of the FLEX 10KE architecture. Each
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
IOE
IOE
Embedded Array Block (EAB)
IOE
IOE
Embedded Array
EAB
EAB
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Logic Array
Block (LAB)
Logic Array
Logic Element (LE)
Local Interconnect
9