EPF10K100EQC240-2N Altera, EPF10K100EQC240-2N Datasheet - Page 11

• Manufacturer Part Number: EPF10K100EQC240-2N
• Description: IC FLEX 10KE FPGA 100K 240-PQFP
• Manufacturer: Altera
• Series: FLEX-10KE®r

Specifications of EPF10K100EQC240-2N

• Number Of Logic Elements/cells: 4992
• Number Of Labs/clbs: 624
• Total Ram Bits: 49152
• Number Of I /o: 189
• Number Of Gates: 257000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Altera Corporation
Figure 2. FLEX 10KE Device in Dual-Port RAM Mode
Notes:
(1)
(2)
EAB Local
Interconnect (2)
All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
EPF10K30E and EPF10K50E devices have 88 EAB local interconnect channels; EPF10K100E, EPF10K130E, and
EPF10K200E devices have 104 EAB local interconnect channels.
wraddress[ ]
rdaddress[ ]
outclocken
inclocken
outclock
inclock
data[ ]
wren
rden
Dedicated Clocks
Dedicated Inputs &
Global Signals
2
4
The EAB can also be used for bidirectional, dual-port memory
applications where two ports read or write simultaneously. To implement
this type of dual-port memory, two EABs are used to support two
simultaneous read or writes.
Alternatively, one clock and clock enable can be used to control the input
registers of the EAB, while a different clock and clock enable control the
output registers (see
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
D
ENA
D
ENA
D
ENA
Q
Q
Q
Figure
D
ENA
D
ENA
Generator
Notes (1)
Row Interconnect
Pulse
Write
Q
2).
Q
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Data In
Read Address
Write Address
Read Enable
Write Enable
RAM/ROM
1,024
2,048
256
Data Out
512
16
8
4
2
D
ENA
Q
4, 8, 16, 32
Column Interconnect
4, 8, 16, 32
4, 8
11