EP4CGX110CF23I7 Altera, EP4CGX110CF23I7 Datasheet - Page 357
EP4CGX110CF23I7
Manufacturer Part Number
EP4CGX110CF23I7
Description
IC CYCLONE IV FPGA 110K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX110CF23I7
Number Of Logic Elements/cells
109424
Number Of Labs/clbs
6839
Total Ram Bits
5490000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4CGX15BN11C8N PDF datasheet
- EP4CGX15BN11C8N PDF datasheet #2
- EP4CGX15BN11C8N PDF datasheet #3
- EP4CGX15BN11C8N PDF datasheet #4
- Current page: 357 of 478
- Download datasheet (13Mb)
Chapter 1: Cyclone IV Transceivers Architecture
Self Test Modes
PRBS
Figure 1–74. PRBS Pattern Test Mode Datapath
Note to
(1) Serial loopback path is optional and can be enabled for the PRBS verifier to check the PRBS pattern
© December 2010 Altera Corporation
Fabric
FPGA
Figure
1–74:
Transmitter Channel PCS
Receiver Channel PCS
Transceiver
Compensation
Tx Phase
Compensation
The incremental pattern generator and verifier are 16-bits wide. The generated pattern
increments from 00 to FF and passes through the TX PCS blocks, parallel looped back
to RX PCS blocks, and checked by the verifier. The pattern is also available as serial
data at the tx_dataout port. The differential output voltage of the transmitted serial
data on the tx_dataout port is based on the selected V
data pattern is not available to the FPGA logic at the receiver for verification.
The following are the transceiver channel configuration settings in this mode:
■
■
■
■
■
The rx_bisterr and rx_bistdone signals indicate the status of the verifier. The
rx_bisterr signal is asserted and stays high when detecting an error in the data.
The rx_bistdone signal is asserted and stays high when the verifier either receives a
full cycle of incremental pattern or it detects an error in the receiver data. You can
reset the incremental pattern generator and verifier by asserting the
tx_digitalreset and rx_digitalreset ports, respectively.
Figure 1–74
modes. The pattern generator is located in TX PCS before the serializer, and PRBS
pattern verifier located in RX PCS after the word aligner.
FIFO
FIFO
Rx
PCS-FPGA fabric channel width: 16-bit
8B/10B blocks: Enabled
Byte serializer/deserializer: Enabled
Word aligner: Automatic synchronization state machine mode
Byte ordering: Enabled
Serializer
shows the datapath for the PRBS, high and low frequency pattern test
Ordering
Byte
Byte
Deserializer
Byte
PRBS, High Freq,
Low Freq Pattern
Encoder
8B/10B
Generator
Decoder
8B/10B
Match
FIFO
Rate
Verifier
PRBS
Aligner
Word
OD
Cyclone IV Device Handbook, Volume 2
settings. The incremental
serializer
Transmitter Channel PMA
Serializer
Receiver Channel
PMA
De-
Receiver
CDR
(1)
1–77
Related parts for EP4CGX110CF23I7
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: