EP3CLS70F484I7N Altera, EP3CLS70F484I7N Datasheet - Page 16
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EP3CLS70F484I7N
Manufacturer Part Number
EP3CLS70F484I7N
Description
IC FPGA CYCIII LS 70K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3CLS70F484I7N.pdf
(274 pages)
Specifications of EP3CLS70F484I7N
Number Of Logic Elements/cells
70208
Number Of Labs/clbs
4388
Total Ram Bits
3068928
Number Of I /o
278
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone III LS
Number Of Logic Blocks/elements
70208
# I/os (max)
278
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
70208
Ram Bits
3068928
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
1–16
Table 1–20. Cyclone III Devices PLL Specifications
Cyclone III Device Handbook, Volume 2
f
t
t
t
t
t
t
t
t
t
t
f
Notes to
(1) V
(2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(3) The V
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.
(5) Peak-to-peak jitter with a probability level of 10
(6) With 100 MHz scanclk frequency.
OUT
OUTDUTY
LOCK
DLOCK
OUTJITTER_PERIOD_DEDC LK
OUTJITTER_CCJ _DEDCLK
OUTJITTER_PERIOD_IO
OUTJITTER_CCJ _IO
PLL_PSERR
ARESET
CONF IGPLL
SC ANC LK
(to global clock)
counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f
jitter of the PLL, when an input jitter of 30 ps is applied.
CC D_P LL
Table
CO
should always be connected to V
frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the V
(5)
Symbol
(5)
1–20:
(5)
(5)
PLL output frequency (–6 speed grade)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
Duty cycle for external clock output (when set to 50%)
Time required to lock from end of device configuration
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
Dedicated clock output period jitter
F
F
Dedicated clock output cycle-to-cycle jitter
F
F
Regular I/O period jitter
F
F
Regular I/O cycle-to-cycle jitter
F
F
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
Time required to reconfigure scan chains for PLLs
scanclk frequency
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
≥ 100 MHz
< 100 MHz
≥ 100 MHz
< 100 MHz
≥ 100 MHz
< 100 MHz
≥ 100 MHz
< 100 MHz
C CINT
through decoupling capacitor and ferrite bead.
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic
(Note 1)
Parameter
(Part 2 of 2)
Chapter 1: Cyclone III Device Data Sheet
© January 2010 Altera Corporation
Min
—
—
—
45
—
—
—
—
—
—
—
—
—
—
—
10
—
—
V CO
specification.
3.5
Switching Characteristics
Typ
—
—
—
50
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
472.5
402.5
Max
450
300
300
650
650
±50
100
55
30
30
75
75
—
—
1
1
C O
SCANCLK
post-scale
cycles
Unit
MHz
MHz
MHz
MHz
mUI
mUI
mUI
mUI
ms
ms
ps
ps
ps
ps
ps
ns
%