EP20K400EBC652-3N Altera, EP20K400EBC652-3N Datasheet - Page 34
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EP20K400EBC652-3N
Manufacturer Part Number
EP20K400EBC652-3N
Description
IC APEX 20KE FPGA 400K 652-BGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K400EBC652-3N
Number Of Logic Elements/cells
16640
Number Of Labs/clbs
1664
Total Ram Bits
212992
Number Of I /o
488
Number Of Gates
1052000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
652-BGA
Family Name
APEX 20K
Number Of Usable Gates
400000
Number Of Logic Blocks/elements
16640
# I/os (max)
488
Frequency (max)
213MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
16640
Ram Bits
212992
Device System Gates
1052000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
652
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
APEX 20K Programmable Logic Device Family Data Sheet
Figure 22. ESB in Single-Port Mode
Notes to
(1)
(2)
34
All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or the chip-wide reset.
APEX 20KE devices have four dedicated clocks.
Figure
address[ ]
outclock
outclken
inclken
inclock
data[ ]
wren
Dedicated Clocks
22:
(2)
2 or 4
Dedicated Inputs &
Global Signals
4
Content-Addressable Memory
In APEX 20KE devices, the ESB can implement CAM. CAM can be
thought of as the inverse of RAM. When read, RAM outputs the data for
a given address. Conversely, CAM outputs an address for a given data
word. For example, if the data FA12 is stored in address 14, the CAM
outputs 14 when FA12 is driven into it.
CAM is used for high-speed search operations. When searching for data
within a RAM block, the search is performed serially. Thus, finding a
particular data word can take many cycles. CAM searches all addresses in
parallel and outputs the address storing a particular word. When a match
is found, a match flag is set high.
diagram.
Note (1)
D
ENA
D
ENA
Q
Q
D
ENA
Generator
Pulse
Write
Q
Figure 23
Data In
Address
Write Enable
RAM/ROM
shows the CAM block
1,024 × 2
2,048 × 1
Data Out
128 × 16
256 × 8
512 × 4
D
ENA
Altera Corporation
Q
to MegaLAB,
FastTrack &
Local
Interconnect